UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE105 Lab Experiments Prelab 8 Multi stage Amplifiers Name Lab Section VCC 5 V ISUP vOUT Q2 VBIAS2 VBIAS1 vin Q1 RS Figure 1 Cascode amplifier with ideal current source 1 The cascode in Figure 1 is biased by an ideal current source Let RS 51 IS 1 10 15 A VA 100 V 200 ISUP 1 mA T 300 K vOUT DC 3 5 V and VBIAS2 2 V Calculate VBIAS1 to match these biasing conditions VBIAS1 1 2 2 What is the gain of this amplifier Av VCC 5 V RC IBIAS1 RREF Q2 vOUT 1 RS Q1 IBIAS2 vOUT 2 vIN Q3 Q4 Figure 2 Multi stage amplifier 3 Now construct a SPICE netlist for the multi stage amplifier shown in Figure 2 Let RC 10 k RS 51 k and RREF 200 Bias transistor Q1 with VBE1 560 mV What is the small signal gain Av1 between vIN and vOUT 1 What is the small signal gain Av2 between vOUT 1 and vOUT 2 Using Av1 and Av2 find the overall gain Av tot between vIN and vOUT 2 Attach the SPICE netlist to the end of this prelab Av1 Av2 Av tot
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