Lecture 21REMINDERS•Review session: Fri. 11/9, 3‐5PM in 306 Soda (HP Auditorium)OUTLINEReview session: Fri. 11/9, 35PM in 306 Soda (HP Auditorium)• Midterm #2 (Thursday 11/15, 3:30‐5PM in Sibley Auditorium)OUTLINE• Frequency Response– Review of basic concepts– high‐frequency MOSFET model– CS stageCG stage–CG stage– Source follower– Cascode stageEE105 Fall 2007 Lecture 21, Slide 1Prof. Liu, UC BerkeleyReading: Chapter 11AvRoll‐Off due to CL• The impedance of CLdecreases at high frequencies, so that it shunts some of the output current to groundthat it shunts some of the output current to ground.LDpCR1=ω0=λLD⎞⎜⎛1⎟⎠⎞⎜⎜⎝⎛−=LDmvCjRgAω1||• In general, if node j in the signal path has a small‐signal resistance of Rjto ground and a capacitance Cjto d th it tib tl t f (RC)1EE105 Fall 2007 Lecture 21, Slide 2Prof. Liu, UC Berkeleyground, then it contributes a pole at frequency (RjCj)‐1Pole Identification Example 10=λ0=λinGpCR11=ωLDpCR12=ωEE105 Fall 2007 Lecture 21, Slide 3Prof. Liu, UC BerkeleyinGLDPole Identification Example 20=λ11inmGpCgR⎟⎟⎠⎞⎜⎜⎝⎛=1||1ωLDpCR2=ωEE105 Fall 2007 Lecture 21, Slide 4Prof. Liu, UC BerkeleyDealing with a Floating Capacitance• Recall that a pole is computed by finding the resistance and capacitance between a node and (AC) GROUNDand capacitance between a node and (AC) GROUND. • It is not str aightforward to compute the pole due to CFin the circuit below, because neither of its terminals isin the circuit below, because neither of its terminals is grounded.EE105 Fall 2007 Lecture 21, Slide 5Prof. Liu, UC BerkeleyMiller’s Theorem • If Av is the voltage gain from node 1 to 2, then a floating impedanceZFcan be converted to twofloating impedance ZF can be converted to two grounded impedances Z1 and Z2:ZVZZVVV⇒− 11121vFFFAZVVZZZZ −=−=⇒=1 21111121FFZVZZVVV 122221=−=⇒−=−EE105 Fall 2007 Lecture 21, Slide 6Prof. Liu, UC BerkeleyvFFFAZVVZZZZ11 2122−−⇒Miller Multiplication• Applying Miller’s theorem, we can convert a floating capacitance between the input and output nodes of p p pan amplifier into two grounded capacitances. • The capacitance at the input node is larger than the l floriginal floating capacitance. FFCjZZ⎞⎛===11111112ωFvvvCAjAA⎠⎞⎜⎝⎛−−−111111ωFFCjZZ11ωEE105 Fall 2007 Lecture 21, Slide 7Prof. Liu, UC Berkeley()FvvFvFCAjACjAZZ−=−=−=11111ωωApplication of Miller’s Theorem0=λ()i=1ωout⎞⎛=1ω()FDmGinCRgR+1ωFDmDoutCRgR⎟⎟⎠⎞⎜⎜⎝⎛+11ωEE105 Fall 2007 Lecture 21, Slide 8Prof. Liu, UC BerkeleyMOSFET Intrinsic CapacitancesThe MOSFET has intrinsic capacitances which affect its performance at high frequencies:p g q1. gate oxide capacitance between the gate and channel,2. overlap and fringing capacitances between the gate and the source/drain regions andsource/drain regions, and3. source‐bulk & drain‐bulk junction capacitances (CSB& CDB).EE105 Fall 2007 Lecture 21, Slide 9Prof. Liu, UC BerkeleyHigh‐Frequency MOSFET Model• The gate oxide capacitance can be decomposed into a capacitance between the gate and the source (C1) andcapacitance between the gate and the source (C1) and a capacitance between the gate and the drain (C2). – In saturat ion, C1≅ (2/3)×Cgate, and C2 ≅ 0. – C1in paralle l with the source overlap/fringing capacitance Æ CGS– C2in paralle l with the drain overlap/fringing capacitance Æ CGDEE105 Fall 2007 Lecture 21, Slide 10 Prof. Liu, UC BerkeleyExampleCS stage…with MOSFET capacitancesexplicitly shownSimplified circuit for high-frequency analysisEE105 Fall 2007 Lecture 21, Slide 11 Prof. Liu, UC BerkeleyTransit Frequency• The “transit” or “cut‐off” frequency, fT, is a measure of the intrinsic speed of a transistor and is defined asof the intrinsic speed of a transistor, and is defined as the frequency where the current gain falls to 1.CtlttfConceptual set-up to measure fTinTminminoutCjgZgII=⎟⎟⎠⎞⎜⎜⎝⎛==ω11inmoutVgI=inmTinTinCgj=⇒⎠⎝ωinininZVI =GSmTCgf =π2EE105 Fall 2007 Lecture 21, Slide 12 Prof. Liu, UC BerkeleyGSCSmall‐Signal Model for CS Stage0=λEE105 Fall 2007 Lecture 21, Slide 13 Prof. Liu, UC Berkeley… Applying Miller’s Theorem ()()inpCRgCR++=11,ω()()GDDminThevCRgCR++1⎞⎛⎞⎛=outp1,ω⎟⎟⎠⎞⎜⎜⎝⎛⎟⎟⎠⎞⎜⎜⎝⎛++GDDmoutDpCRgCR11,EE105 Fall 2007 Lecture 21, Slide 14 Prof. Liu, UC BerkeleyNote that ωp,out> ωp,inDirect Analysis of CS Stage• Direct analysis yields slightly different pole locations and an extra zero:and an extra zero:mg=ωXYzC=1ωω()()()()outXYDinThevThevXYDmoutXYDinThevThevXYDmpCCRCRRCRgCCRCRRCRg++++++++=111ω()()()outinXYoutXYinDThevoutXYDinThevThevXYDmpCCCCCCRRCCCCg++=2ωEE105 Fall 2007 Lecture 21, Slide 15 Prof. Liu, UC BerkeleyI/O Impedances of CS Stage0=λ11()[]GDDmGSinCRgCjZ++≈11ω[]DDBGDoutRCCjZ ||1+=ωEE105 Fall 2007 Lecture 21, Slide 16 Prof. Liu, UC BerkeleyCG Stage: Pole Frequencies1CG stage with MOSFET capacitances shownXSXpCgR⎟⎠⎞⎜⎜⎝⎛=1||1,ω0=λmg⎠⎝SBGSXCCC+=Y1=ωYDYpCR,ωDBGDYCCC+=EE105 Fall 2007 Lecture 21, Slide 17 Prof. Liu, UC BerkeleyDBGDYCCC+AC Analysis of Source Follower• The transfer function of a source follower can be0=λsource follower can be obtained by direct AC analysis, similarly as for th itt fll (fthe emitter follower (ref. Lecture 14, Slide 6)()1+ωCjGS()SCCCCCCRa++=()() ()112+++=ωωωjbjagjvvminout()SBGDGDSSBGSSBGDGSGDmgCCCRbCCCCCCga++=++=EE105 Fall 2007 Lecture 21, Slide 18 Prof. Liu, UC BerkeleymgExample()1CjGS()() ()112+++=ωωωjbjagjvvmGSinoutR[]221122111111))((DBGDSBGDDBGDSBGSGDGSGDmSCCCCbCCCCCCCgRa+++++++=EE105 Fall 2007 Lecture 21, Slide 19 Prof. Liu, UC Berkeley122111mDBGDSBGDGDSgCCCCCRb++++=Source Follower: Input Capacitance• Recall that the voltage gain of a source follower isSvRRA+=1SmRg+Follower stage with MOSFET capacitances shown0=λ• CXYcan be decomposed into CdCh i d0λ()CCXand CYat the input and output nodes, respectively:()SmGSGSvXRgCCAC+=−=11SmGSGDinRgCCC++=1EE105 Fall 2007 Lecture 21, Slide 20 Prof. Liu, UC BerkeleyExample0≠λ()11||11GSGDinCrrgCC++=EE105 Fall 2007 Lecture 21, Slide 21 Prof. Liu, UC Berkeley()211||1OOmrrg+Source Follower: Output Impedance• The output impedance of fll b0=λa source follower can be obtained by direct AC analysis, similarly as for the emitter follower (ref. Lecture 14, Slide 9)CRj+1mGSGSGXXgCjCRjiv++=ωω1EE105 Fall 2007 Lecture 21, Slide 22 Prof. Liu, UC
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