UNIVERSITY OF CALIFORNIA AT BERKELEYCollege of EngineeringDepartment of Electrical Engineering and Computer SciencesDiscussion Notes: MOSCAPFriday, October 26, 2007EE 105 Fall 2007Prof. LiuThese discussion notes were originally written for Spring 2007. The figures are from the Howe and Sodinilecture slides, so some notation is different (e.g. threshold voltage is VT nrather than VT H). The sampleproblem covers a few things we haven’t taught this semester (namely calculating VF B).Note that φsis the surface potential (the potential at x = 0) and φpis just φBas we’ve been using theterm this semester.1 The MOS CapacitorLast week, the lectures covered the operation of the MOS capacitor. Let’s briefly review the material covered,in particular the regions of operation (i.e. accumulation, depletion, and inversion) and how to obtain aqualitative understanding of how the capacitance arrives in these regions of op eration. I will assume an n+gate an p-type substrate for this discussion.1.1 AccumulationRecall that accumulation occurs when we set VGB< VF B, pulling the gate to a potential below the substrate.From the graph of potential across the MOS structure (see Figure 1), we know thatdVdxis positive, meaningE(x), the electric field, is negative, or pointing in the negative x direction. This causes holes to accumulateat the top of the substrate and electrons to accumulate at the bottom of the n+ gate.Figure 1: Potential across a MOS capacitor in accumulation.This is exactly the behavior we imagine from a parallel plate capacitor. If we incrementally change VGBwhile the device is in accumulation, we’re incrementally changing the slope of V , meaning we’re incrementallychanging E(x), which is a constant value for a given VF B. For a parallel plate capacitor, we have C =²d(capacitance per unit area), where ² is the permittivity of the dielectric material and d is the distance betweenthe separated charges. In this case, we have ² = ²oxand d = tox, so the capacitance in accumulation isCox=²oxtox.1.2 DepletionDepletion occurs when VF B< VGB< VT n. Figure 2 shows the potential across the MOS capacitor whenoperating in the depletion mo de.1Figure 2: Potential across a MOS capacitor in depletion.We can see that for −tox< x < 0, the potential is still linear, as it was in accumulation. Hence, ourphysical interpretation would be that we still have the presence of Coxin the capacitance of the entirestructure. However, we also have a depletion region now, meaning we have a depletion capacitance (Howeand Sodini call this Cb, presumably for bulk capacitance, so I will stick with that notation).We know that the depletion region will have a certain width Xd, which depends on the applied VGB. Al-though Xd(VGB) is a rather complicated function, we know that for a given depletion width, the capacitancecan be written as Cb=²sXd. Since Cbis in series with Cox(Coxrepresents the capacitance from x = −toxtox = 0, while Cbrepresents the capacitance from x = 0 to x = Xd), we can write C =CoxCbCox+Cb.Since Coxis a constant, we have the capacitance varying as a function of Cb. Consider qualitativelyas VGBincreases, the depletion width, Xd, increases, meaning that the capacitance Cb∝1Xddecreases.Recall that for series capacitors, as one capacitance gets larger than the other, the equivalent capacitanceapproaches that of the smaller capacitor (think of the limiting case where the capacitance goes to zero).Hence, we would expect that the capacitance decreases as VGBincreases while in the depletion mode ofoperation, and our intuition here corresponds with the actual device behavior.1.3 InversionInversion occurs when VGB> VT n, where we define VT nto be the threshold voltage of the device. Wedefine VT nto be the voltage where φs= −φp(the exact reasons for this are related to energy bands andband bending, which is a topic for EE130). The simplified version of what is happening is that the siliconnear the surface of the device (i.e. around x = 0) becomes inverted, meaning it actually starts acting liken-type silicon, despite being doped p-type. What this means is that electrons form at the surface, creatingan inversion layer of charge.Since this charge grows exponentially with the surface potential φsonce VGBexceeds VT n(see Eq. 3.135in Howe and Sodini), we can make the approximation that φsremains approximately constant once thedevice hits inversion. This means that the depletion region stops growing and stays at Xd,maxwhile theinversion charge is free to grow very large as VF Bis increased.Having this foundation, we can once again use our physical intuition to determine the capacitance of thedevice. We know that if we change the voltage by a small amount dV , the depletion region won’t grow at all,meaning there is no depletion capacitance in inversion. The positive charge in the n+ gate and the inversioncharge at the surface of the substrate will change, though. Thus, we have C = Cox=²oxtox.1.4 Frequency dependence (Optional)There is a minor point to be made about the behavior of the device in inversion under high frequency andlow frequency conditions. The electrons in the inversion layer must be generated somehow, as there aren’tsufficient free electrons in a p-type substrate to form an inversion layer without some excitation. For a MOS2capacitor as we have shown in our diagrams, the electrons are generated slowly by thermal excitation. Fora high frequency signal, though, there is not sufficient time for this generation to occur, so we end up withCb(from our discussion of depletion) dominating the capacitance.For MOS transistors, this isn’t a problem, because we have n+ source and drain diffusions that have anample supply of electrons to fill the inversion layer (called a channel once we talk about transistors). Whatthis means is that under high frequency operation, instead of the capacitance jumping back up to Coxwhenthe device goes into inversion, it remains at the minimum value it reaches in depletion. Under low frequencyoperation, or when we have a source and drain, the capacitance does jump back up to Cox.1.5 Example ProblemLet’s do an example problem. Assume we have a MOS capacitor with n+ polysilicon as the gate and p-typesilicon as the substrate. Take Na= 1017cm−3for the substrate and tox= 20 nm.For this structure, we can compute φn+and φp, the potentials of the gate and the substrate, respectively.From this, we can compute VF B= −(φn+− φp).φn+= 550mVφp= −60
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