UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Discussion Notes MOSCAP Friday October 26 2007 EE 105 Prof Liu Fall 2007 These discussion notes were originally written for Spring 2007 The figures are from the Howe and Sodini lecture slides so some notation is different e g threshold voltage is VT n rather than VT H The sample problem covers a few things we haven t taught this semester namely calculating VF B Note that s is the surface potential the potential at x 0 and p is just B as we ve been using the term this semester 1 The MOS Capacitor Last week the lectures covered the operation of the MOS capacitor Let s briefly review the material covered in particular the regions of operation i e accumulation depletion and inversion and how to obtain a qualitative understanding of how the capacitance arrives in these regions of operation I will assume an n gate an p type substrate for this discussion 1 1 Accumulation Recall that accumulation occurs when we set VGB VF B pulling the gate to a potential below the substrate From the graph of potential across the MOS structure see Figure 1 we know that dV dx is positive meaning E x the electric field is negative or pointing in the negative x direction This causes holes to accumulate at the top of the substrate and electrons to accumulate at the bottom of the n gate Figure 1 Potential across a MOS capacitor in accumulation This is exactly the behavior we imagine from a parallel plate capacitor If we incrementally change VGB while the device is in accumulation we re incrementally changing the slope of V meaning we re incrementally changing E x which is a constant value for a given VF B For a parallel plate capacitor we have C d capacitance per unit area where is the permittivity of the dielectric material and d is the distance between the separated charges In this case we have ox and d tox so the capacitance in accumulation is ox Cox tox 1 2 Depletion Depletion occurs when VF B VGB VT n Figure 2 shows the potential across the MOS capacitor when operating in the depletion mode 1 Figure 2 Potential across a MOS capacitor in depletion We can see that for tox x 0 the potential is still linear as it was in accumulation Hence our physical interpretation would be that we still have the presence of Cox in the capacitance of the entire structure However we also have a depletion region now meaning we have a depletion capacitance Howe and Sodini call this Cb presumably for bulk capacitance so I will stick with that notation We know that the depletion region will have a certain width Xd which depends on the applied VGB Although Xd VGB is a rather complicated function we know that for a given depletion width the capacitance can be written as Cb X sd Since Cb is in series with Cox Cox represents the capacitance from x tox to Cb x 0 while Cb represents the capacitance from x 0 to x Xd we can write C CCoxox C b Since Cox is a constant we have the capacitance varying as a function of Cb Consider qualitatively as VGB increases the depletion width Xd increases meaning that the capacitance Cb X1d decreases Recall that for series capacitors as one capacitance gets larger than the other the equivalent capacitance approaches that of the smaller capacitor think of the limiting case where the capacitance goes to zero Hence we would expect that the capacitance decreases as VGB increases while in the depletion mode of operation and our intuition here corresponds with the actual device behavior 1 3 Inversion Inversion occurs when VGB VT n where we define VT n to be the threshold voltage of the device We define VT n to be the voltage where s p the exact reasons for this are related to energy bands and band bending which is a topic for EE130 The simplified version of what is happening is that the silicon near the surface of the device i e around x 0 becomes inverted meaning it actually starts acting like n type silicon despite being doped p type What this means is that electrons form at the surface creating an inversion layer of charge Since this charge grows exponentially with the surface potential s once VGB exceeds VT n see Eq 3 135 in Howe and Sodini we can make the approximation that s remains approximately constant once the device hits inversion This means that the depletion region stops growing and stays at Xd max while the inversion charge is free to grow very large as VF B is increased Having this foundation we can once again use our physical intuition to determine the capacitance of the device We know that if we change the voltage by a small amount dV the depletion region won t grow at all meaning there is no depletion capacitance in inversion The positive charge in the n gate and the inversion ox charge at the surface of the substrate will change though Thus we have C Cox tox 1 4 Frequency dependence Optional There is a minor point to be made about the behavior of the device in inversion under high frequency and low frequency conditions The electrons in the inversion layer must be generated somehow as there aren t sufficient free electrons in a p type substrate to form an inversion layer without some excitation For a MOS 2 capacitor as we have shown in our diagrams the electrons are generated slowly by thermal excitation For a high frequency signal though there is not sufficient time for this generation to occur so we end up with Cb from our discussion of depletion dominating the capacitance For MOS transistors this isn t a problem because we have n source and drain diffusions that have an ample supply of electrons to fill the inversion layer called a channel once we talk about transistors What this means is that under high frequency operation instead of the capacitance jumping back up to Cox when the device goes into inversion it remains at the minimum value it reaches in depletion Under low frequency operation or when we have a source and drain the capacitance does jump back up to Cox 1 5 Example Problem Let s do an example problem Assume we have a MOS capacitor with n polysilicon as the gate and p type silicon as the substrate Take Na 1017 cm 3 for the substrate and tox 20 nm For this structure we can compute n and p the potentials of the gate and the substrate respectively From this we can compute VF B n p n 550mV Na 420 mV ni n p 550 420 970 mV p 60 mV log VF B Now that we have the flatband voltage we can also compute the threshold voltage ox 2 172 6 nF cm tox q 1 VF B 2 p 2q s Na 2 p
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