EECS 105 Spring 2004 Lecture 31 EECS 105 Spring 2004 Lecture 31 Prof J S Smith Reading z We are starting on chapter 9 multi stage amplifiers Lecture 31 Homework Make sure you do problem P8 18 not example E8 18 Prof J S Smith Department of EECS University of California Berkeley Department of EECS University of California Berkeley Prof J S Smith EECS 105 Spring 2004 Lecture 31 Prof J S Smith EECS 105 Spring 2004 Lecture 31 Context Lecture Outline We are looking at more examples of single transistor active circuits and typical design problems and starting multi stage amplifiers z z z z z z Department of EECS University of California Berkeley Department of EECS Example Voltage regulator Transimpedance Amplifier Source Follower Current Mirror Push Pull Amplifier Multistage Amplifiers University of California Berkeley 1 EECS 105 Spring 2004 Lecture 31 Prof J S Smith EECS 105 Spring 2004 Lecture 31 Voltage regulator z z z Shunt regulators One problem that often arises is that of taking an imperfect power supply and creating a regulated power supply For example Electrically programmable memories are often very sensitive to voltage There are two basic solutions to the voltage regulation problem Prof J S Smith z Series regulators Shunt regulators In a shunt regulator a higher voltage unregulated supply which has some source resistance is shunted to ground by a parallel device in order to keep the regulated voltage from going too high Vunregulated Vregulated In a shunt regulator the controlling device can even be turned off so that the power lost can be reduced to zero in the case where power is most critical but the power lost can be high if the unregulated voltage goes up or if the source impedance is low The power Isource Iload Vunregulated is lost And there are Analog and Switched solutions Department of EECS University of California Berkeley Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 31 Prof J S Smith EECS 105 Spring 2004 Lecture 31 Prof J S Smith Series regulators z Uses In a series regulator a higher voltage unregulated supply is reduced and regulated by putting a device in series with the source Vunregulated Vregulated z For a battery powered device you would want to use a series regulator to avoid draining the battery If the source of power can t be depleted you might want to use a shunt regulator so that losses only occur when you are trying to throw away power anyway In this shunt regulator we need the unregulated voltage to be sufficiently higher than the regulation point so that the device works properly and the power Iload Vunregulated Vregulated is lost Department of EECS z Solar powered device or array Passive RFID tags Wind or Small hydroelectric What does an automobile use University of California Berkeley Department of EECS University of California Berkeley 2 EECS 105 Spring 2004 Lecture 31 Prof J S Smith EECS 105 Spring 2004 Lecture 31 Prof J S Smith Series regulators z Load line diagram Here is a linear series regulator using a common gate connected transistor Since the drain current is relatively independent of the drain voltage when the transistor is in saturation regulation can be good as long as sufficient drop is available z In order to find the operating point for the regulator at a given supply voltage we draw a load line for the resistor and the current available from the resistor as a function of VDD VS Vregulated Vunregulated IN For no load current the point where the current available the resistor is consumed by the transistor is the operating point IR R In this series regulator we need the unregulated voltage to be sufficiently higher than the regulation point so that the transistor will be in forward saturation or the regulation will be poor The power Iload Vunregulated Vregulated is lost For large currents with devices that need approximately a volt drop across them this is a large loss VTn VS VDD Department of EECS University of California Berkeley Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 31 Prof J S Smith EECS 105 Spring 2004 Lecture 31 Prof J S Smith Shunt regulators z Regulation In this shut regulator a common source device is used as an active load configuration to pull down excessive voltage at the load z Two questions that we can ask about regulation VS IN If the supply voltage varies how much does the output voltage vary If the load current varies how much does the output voltage vary If the load current is held constant a the change in the output voltages is given by the variation in the supply voltage divided down by a resistive divider z Since the drain current is a relatively insensitive function of the drain voltage we get that the change in the drain current is just iD vGS g m So the FET in small signal looks 1 like a resistor with a resistance Rn g z VDD Department of EECS University of California Berkeley Department of EECS m University of California Berkeley 3 EECS 105 Spring 2004 Lecture 31 Prof J S Smith shunt regulator z z So we have EECS 105 Spring 2004 Lecture 31 Add Voltage gain common gate stage 1 VDD 1 gm 1 Vs R 1 gm R gm z L 1 gm 1 1 R gm gm 1 R IN VS R2 VDD V2 As VDD goes up the current through the PMOS transistor goes up i v g so the small signal voltage current sees a source impedance ZO If we add gain in the small signal voltage at the gate of the FET we can improve regulation RS Let s hold VDD constant and vary the load current by a small amount In small signal this looks like a current being divided between two resistors to SS ground So a small change in the output I R Prof J S Smith p R Rg m 1 gs mp v2 i2 R2 Rvgs g mp Rg mp VDD VDD 1 1 Vs 1 g m RA 1 g m Rs g mp R2 In both cases the regulation is poor because gm is relatively small Department of EECS University of California Berkeley Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 31 Prof J S Smith EECS 105 Spring 2004 Lecture 31 Prof J S Smith Adding voltage gain z Transimpedance Amplifier If we add gain in the small signal voltage at the gate of the FET we can improve regulation Figure 22 8 A VS VR VDD 1 Vs 1 g m RA Department of EECS IN VDD z The transimpedance is AR for A 1 VDD VR University of California Berkeley Department of EECS id g 1 vout W1 L3 W3mL21 iin g m 2W3 L1 id W1L3 University of California Berkeley 4 EECS 105 Spring 2004 Lecture 31 Prof J S Smith EECS 105 Spring 2004 Lecture 31 Prof J S Smith Source Follower Current Mirror Figure 22 11 z Gain
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