EECS 105 Spring 2002 Lecture 24 R T Howe Lecture 24 Last time Multi stage amplifiers voltage transconductance Today Cascode merged CS CG cascade Dept of EECS University of California Berkeley EECS 105 Spring 2002 Lecture 24 R T Howe CG Cascade Sharing a Supply First stage has no current supply of its own its output resistance is modified Dept of EECS University of California Berkeley EECS 105 Spring 2002 Lecture 24 R T Howe Multistage Amplifier Design Examples Start with basic two stage transconductance amplifier Why do this combination Dept of EECS University of California Berkeley EECS 105 Spring 2002 Lecture 24 R T Howe Two Stage Amplifier Topology Direct DC connection use NMOS then PMOS Dept of EECS University of California Berkeley EECS 105 Spring 2002 Lecture 24 R T Howe Current Supply Design Assume that the reference is a sink set by a resistor Must mirror the reference current and generate a sink for iSUP 2 Dept of EECS University of California Berkeley EECS 105 Spring 2002 Lecture 24 R T Howe Use Basic Current Supplies Dept of EECS University of California Berkeley EECS 105 Spring 2002 Lecture 24 R T Howe Complete Amplifier Topology What s missing The device dimensions and the bias voltage and reference resistor Dept of EECS University of California Berkeley EECS 105 Spring 2002 Lecture 24 R T Howe The Cascode Configuration Common source common gate cascade is one version of a cascode all have shared supplies DC bias Two port model first stage has no current supply of its own Dept of EECS University of California Berkeley EECS 105 Spring 2002 Lecture 24 R T Howe Cascode Two Port Model CS1 CG2 Output resistance of first stage Rout CS R down CS ro1 Why is the cascode such an important configuration Dept of EECS University of California Berkeley EECS 105 Spring 2002 Lecture 24 R T Howe Miller Capacitance of Input Stage Find the Miller capacitance for Cgd1 Input resistance to common gate second stage is low gain across Cgd1 is small Dept of EECS University of California Berkeley EECS 105 Spring 2002 Lecture 24 R T Howe Two Port Model with Capacitors Miller capacitance C M 1 AvC gd 1 C gd 1 Dept of EECS University of California Berkeley EECS 105 Spring 2002 Lecture 24 R T Howe Other Cascode Configurations Basic configuration transconductance stage followed by current buffer CEn CGn Dept of EECS CSn CB CSp CGp University of California Berkeley
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