17 High to Low Propagation Delay tPHL VIN switches instantly from low to high Driver transistor n channel immediately switches from cutoff to saturation the p channel pull up switches from triode to cutoff Circuit during high to low transition Hand Calculation of tPHL The output voltage decreases linearly over 0 t tPHL if we assume that the MOSFET remains saturated vOUT t p channel MOSFET is cutoff IDn VOH slope dvOUT dt vOUT t VOH 2 CL CG CP VIN t 0 VOH 0 The voltage on the load capacitor at t 0 was VOH since n channel MOSFET is saturated initially and the input voltage is a constant the drain current is initially IDn sat for VGS V The high to low propagation delay tPHL is by definition the time required for VOUT to reach VOH 2 dvOUT I Dn sat d QL dt C G C P dt CG C P tPHL t The high to low propagation delay is given by dv OUT V OH 2 V OH I Dn sat dt t PHL CG CP Solving for the delay C G C P V OH 2 t PHL 2 n C ox W 2L n V OH V Tn EECS 105 Fall 1998 Lecture 17 EECS 105 Fall 1998 Lecture 17 Graphical Interpretation Low to High Propagation Delay tPLH The n channel driver remains saturated throughout the first half of the transition from high to low ID For the low to high transition the n channel device is cutoff and the p channel MOSFET is initially saturated and supplying IDp sat to charge up the gate and parasitic capacitances VOUT VDD t 0 VIN VOH t tPHL VSGp VOH t 0 VIN 0V VOH 2 0 0 VOH 2 VOH a VOUT 0 0 VIN 0 V t tPHL IDp b note that the characteristics above are not for a square law MOSFET which would enter the triode region for VOUT VOH VTn the error is not large enough to matter for hand calculations in any case Therefore C G C P V OH 2 t PLH 2 p C ox W 2L p V OH V Tp In order to have identical propagation delays the width to length ratio of the pchannel pull up must be twice that of the n channel driver in order to compensate for the lower hole mobility in the channel EECS 105 Fall 1998 Lecture 17 EECS 105 Fall 1998 Lecture 17 Power Dissipation Power cont Energy from power supply needed to charge up the capacitor E charge V 2 i t dt V Q V C G C P Practical numbers CL 50 fF f 200 MHz V 3 V Ngates 5 x 105 P 45 W note that the real average depends on the average number switching per clock cycle Comparing Technologies the power delay product Energy stored in the capacitor Logic families are often compared by considering the product of the dynamic power dissipation and the propagation delay 1 2 E store C G C P V 2 Energy lost in p channel MOSFET during charging 2 1 E diss E charge E store C G C P V 2 During discharge the n channel MOSFET driver dissipates an identical amount of energy If the charge discharge cycle is repeated f times second where f is the clock frequency the dynamic power dissipation is 2 C L C p V 2 PDP Pt P C L C p V f 2 1 k V V Tn 2 N where V has been substituted for VOH to achieve a more universal result For V VTn 2 CL Cp V f PDP kN 2 P 2E diss f C G C P V f In practice many gates don t change state every clock cycle which lowers the power dissipation Additional source of dissipation power flow from V to ground when both transistors are saturated Can be significant but hard to estimate by hand Typical number 25 of dynamic power dissipation EECS 105 Fall 1998 Lecture 17 EECS 105 Fall 1998 Lecture 17 CMOS Static Logic Gates CMOS NAND Gate Static logic levels remain valid so long as power is supplied NOR and NAND gates Qualitative description Find transfer curve for case where VA VB and both transition from 0 to 5 V VDD Transistors M1 and M2 are in series and have the same current however they do not have the same gate source bias M4 A M3 B VDD M2 VOUT M1 B A VM M3 M4 ID VM VM VGS1 VM M2 a M1 VDS1 VDD VGS2 VM VDS1 ID1 ID2 M3 A M4 VDS a A B b B M2 VOUT M1 b EECS 105 Fall 1998 Lecture 17 EECS 105 Fall 1998 Lecture 17 MOSFETs in Series MOSFETs in Series Cont Transistors M1 and M2 are in series with the same gate voltage for the case where the inputs are tied together A B At VA VB VM the cross section through M1 M2 is VM VOUT source VM gate gate M1 M2 n L1 L2 a drain VM M1 source VM gate gate M1 M2 L1 L2 drain b VA VB Transistor M1 is in triode and M2 is saturated From the cross section the drain of M1 source of M2 can be eliminated without affecting anything the two MOSFETs can be merged into a composite transistor with L1 L2 2 Ln Solving for VM for the case where VA VB note that the two p channel devices are in parallel and have an effective width of W3 W4 2 Wp M2 ground drain current is the same through each device what is the effective value of kP kp 2k p V Tn 2 V DD V Tp V Tn V DD V Tp kn 2 kn V M 2k p kp 1 1 2 kn 2 kn where kn nCox Wn Ln and kp pCox Wp Lp We could optimize VM VDD 2 but there is another switching condition to consider EECS 105 Fall 1998 Lecture 17 EECS 105 Fall 1998 Lecture 17
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