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Berkeley ELENG 105 - High-to-Low Propagation Delay

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EECS 105 Fall 1998Lecture 17High-to-Low Propagation Delay tPHL ■ VIN switches instantly from low to high. Driver transistor (n-channel) immediately switches from cutoff to saturation; the p-channel pull-up switches from triode to cutoff. ■ Circuit during high-to-low transition:■ The voltage on the load capacitor at t = 0- was VOH; since n-channel MOSFET is saturated initially and the input voltage is a constant, the drain current is initially IDn(sat) for VGS = V+.■ The high-to-low propagation delay tPHL is (by definition) the time required for VOUT to reach VOH / 2:+_CL = CG + CPvOUT (t)VIN (t > 0) = VOHIDn (p-channel MOSFET is cutoff)dvOUTdt-----------------ddt-----QLCGCP+---------------------IDn sat()–CGCP+-----------------------==17EECS 105 Fall 1998Lecture 17Hand Calculation of tPHL■ The output voltage decreases linearly over 0 < t < tPHL if we assume that the MOSFET remains saturated:■ The high-to-low propagation delay is given by:Solving for the delay:t vOUT (t)0VOHVOH / 2tPHLslope = dvOUT / dtdvOUTdt-----------------VOH2⁄()VOH–tPHL-----------------------------------------IDn sat()–CGCP+-----------------------==tPHLCGCP+()VOH2⁄()µnCoxW 2L⁄()nVOHVTn–()2---------------------------------------------------------------------------=EECS 105 Fall 1998Lecture 17Graphical Interpretation■ The n-channel driver remains saturated throughout the first half of the transition from high-to-low...note that the characteristics above are not for a square-law MOSFET, which would enter the triode region for VOUT < VOH - VTn; the error is not large enough to matter for hand calculations in any caseID2t = tPHLt = 0+t = 0−VIN = 0VVIN = VOHtPHLt2(a) (b)VOUTVOHVOHVOUTVOHVOH0000EECS 105 Fall 1998Lecture 17Low-to-High Propagation Delay tPLH■ For the low-to-high transition, the n-channel device is cutoff and the p-channel MOSFET is initially saturated and supplying - IDp(sat) to charge up the gate and parasitic capacitances. ■ Therefore,In order to have identical propagation delays, the width-to-length ratio of the p-channel pull-up must be twice that of the n-channel driver, in order to compensate for the lower hole mobility in the channel.VDDVIN = 0 V+_VSGp- IDptPLHCGCP+()VOH2⁄()µpCoxW 2L⁄()pVOHVTp+()2---------------------------------------------------------------------------=EECS 105 Fall 1998Lecture 17Power Dissipation■ Energy from power supply needed to charge up the capacitor:■ Energy stored in the capacitor:■ Energy lost in p-channel MOSFET during charging:During discharge, the n-channel MOSFET driver dissipates an identical amount of energy. If the charge/discharge cycle is repeated f times/second, where f is the clock frequency, the dynamic power dissipation is:In practice, many gates don’t change state every clock cycle, which lowers the power dissipation■ Additional source of dissipation: power flow from V+ to ground when both transistors are saturated. Can be significant, but hard to estimate by hand. Typical number: 25% of dynamic power dissipation.EchargeV+it()dt∫V+QV+()2CGCP+()===Estore=12---CGCP+()V+()2EdissEchargeEstore+12---CGCP+()V+()2==P 2Ediss()f⋅CGCP+()V+()2f==EECS 105 Fall 1998Lecture 17Power (cont.)■ Practical numbers: CL = 50 fF, f = 200 MHz, V+ = 3 V, Ngates = 5 x 105 P = 45 W ! (note that the real average depends on the average number switching per clock cycle)Comparing Technologies -- the power-delay product* Logic families are often compared by considering the product of the dynamic power dissipation and the propagation delay:where V+ has been substituted for VOH to achieve a more universal result.* For V+ >> VTn, PDP PtPCLCp+()V+()2fCLCp+()V+2⁄()12---kNV+VTn–()2--------------------------------------------≅=PDPCLCp+()2V+fkN-------------------------------------≅EECS 105 Fall 1998Lecture 17CMOS Static Logic Gates■ “Static” -- logic levels remain valid so long as power is supplied■ NOR and NAND gatesVOUTVDDVDDBAM1M3M4M2M1M2M3M4AABAB(a)(b)B+_VOUT+_EECS 105 Fall 1998Lecture 17CMOS NAND Gate■ Qualitative descriptionFind transfer curve for case where VA = VB and both transition from 0 to 5 V■ Transistors M1 and M2 are in series and have the same current; however, they do not have the same gate-source biasVDDVDS1M3M4M2M1VMVMVM(a)IDID1 = ID2VGS2 = VM − VDS1VGS1 = VMVDS(b)+−EECS 105 Fall 1998Lecture 17MOSFETs in Series■ Transistors M1 and M2 are “in series” with the same gate voltage, for the case where the inputs are tied together (A = B) drain current is the same through each device ... what is the effective value of kP?groundVOUT VA = VBM1M2EECS 105 Fall 1998Lecture 17MOSFETs in Series (Cont.)■ At VA = VB = VM, the cross section through M1 - M2 is: ■ Transistor M1 is in triode and M2 is saturated. From the cross section, the drain of M1/ source of M2 can be eliminated without affecting anything --> the two MOSFETs can be merged into a composite transistor with L1 + L2 = 2 Ln■ Solving for VM for the case where VA = VB (note that the two p-channel devices are in parallel and have an effective width of W3 + W4 = 2 Wp where kn = µnCox (Wn/Ln) and kp = µpCox (Wp/Lp)We could optimize VM = VDD/2, but there is another switching condition to consider,,,,,,,,gatesourcegatedrainVMVMVML1L2,,,,,,,,,,,,,,gatesourcegatedrainVML1L2(b)(a)n+M1M2M1M2VMVTn2kpkn2⁄------------ VDDVTp+()+12kpkn2⁄------------+-----------------------------------------------------------------VTn2kpkn-----


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Berkeley ELENG 105 - High-to-Low Propagation Delay

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