CMOS Amplifiers EE105 Spring 2007 Microelectronic Devices and Circuits Lecture 6 CMOS Amplifiers General Considerations Common Source Stage Common Gate Stage Source Follower Summary and Additional Examples 2 Lecture Outline Voltage Amplifier In an ideal voltage amplifier the input impedance is infinite and the output impedance zero But in reality input or output impedances depart from their ideal values 3 4 Input Output Impedances Rx Common Source Stage Vx ix 0 Av gm RD The figure above shows the techniques of measuring input and output impedances Av 2 nCox W I D RD L 5 6 CS Stage with 0 Operation in Saturation Condition for M1 in saturation Vout Vin VTH VDD RD I D VGS VTH Av g m RL In order to maintain operation in saturation Vout cannot fall below Vin by more than one threshold voltage The condition above ensures operation in saturation Rin Rout RL 7 8 CS Stage with 0 CS Gain Variation with Channel Length Av gm RL rO Rin Av Rout RL rO However channel length modulation leads to finite output resistance ro which is in parallel with the load resistance RL 9 MOS Biasing W L 2 nCoxWL ID ID 2 nCox Since is inversely proportional to L the intrinsic voltage gain actually becomes proportional to the square root of L 10 Self Biased MOS Stage R1 VDD VGS I D RS R1 R2 W 1 2 I D nCox VGS VTH L 2 I D RD VGS RS I D VDD 1 W 2 I D nCox VGS VTH 2 L 2 unknows VGS I D 2 equations RV VGS V1 VTH V12 2V1 2 DD VTH R1 R2 1 V1 W nCox RS L Voltage at X is determined by VDD R1 and R2 VGS can be found using the equation above and ID can be found by using the NMOS current equation The circuit above is analyzed by noting M1 is in saturation and no potential drop appears across RG 11 12 Current Sources CS Stage with Current Source Load Av g m1 rO1 rO 2 Rout rO1 rO 2 When in saturation region a MOSFET behaves as a current source NMOS draws current from a point to ground sinks current whereas PMOS draws current from VDD to a point sources current 13 PMOS CS Stage with NMOS as Load To alleviate the headroom problem an active current source load is used This is advantageous because a current source has a high output resistance and can tolerate a small voltage drop across it 14 CS Stage with Diode Connected Load Av g m 2 rO1 rO 2 1 rO 2 rO1 Av g m1 gm2 W L 1 1 Av g m1 gm2 W L 2 Similarly with PMOS as input stage and NMOS as the load the voltage gain is the same as before Lower gain but less dependent on process parameters 15 16 CS Stage with Degeneration CS Stage with Diode Connected PMOS Device 1 Av g m 2 ro1 ro 2 g m1 Av 0 Note that PMOS circuit symbol is usually drawn with the source on top of the drain 17 RD 1 RS gm Similar to bipolar counterpart when a CS stage is degenerated its gain I O impedances and linearity change 18 CS Stage with Gate Resistance Example of CS Stage with Degeneration VRG 0 Av RD 1 1 g m1 g m 2 A diode connected device degenerates a CS stage 19 Since at low frequencies the gate conducts no current gate resistance does not affect the gain or I O impedances 20 Output Impedance of CS Stage with Degeneration Output Impedance Example I rout gmrO RS rO 1 1 Rout rO1 1 g m1 gm2 gm2 Similar to the bipolar counterpart degeneration boosts output impedance 21 Output Impedance Example II When 1 gm is parallel with rO2 we often just consider 1 gm CS Core with Biasing Av Rout g m1rO1rO 2 rO1 In this example the impedance that degenerates the CS stage is rO instead of 1 gm in the previous example 22 23 RD R1 R2 1 RG R1 R2 RS gm Av g m R D Degeneration is used to stabilize bias point and a bypass capacitor can be used to obtain a larger smallsignal voltage gain at the frequency of interest 24 Common Gate Stage Signal Levels in CG Stage Av g m RD Common gate stage is similar to common base stage a rise in input causes a rise in output So the gain is positive In order to maintain M1 in saturation the signal swing at Vout cannot fall below Vb VTH 25 I O Impedances of CG Stage Rin 1 gm 0 26 CG Stage with Source Resistance Rout RD Av The input and output impedances of CG stage are similar to those of CB stage RD 1 RS gm When a source resistance is present the voltage gain is equal to that of a CS stage with degeneration only positive 27 28 Generalized CG Behavior Example of CG Stage Rout 1 g m rO RS rO When a gate resistance is present it does not affect the gain and I O impedances since there is no potential drop across it at low frequencies The output impedance of a CG stage with source resistance is identical to that of CS stage with degeneration vout g m1 RD vin 1 g m1 g m 2 RS 29 CG Stage with Biasing 1 Rout g m1rO1 RS rO1 RD gm2 Diode connected M2 acts as a resistor to provide the bias current 30 Source Follower Stage R 1 gm vout 3 gmRD vin R3 1 gm RS R1 and R2 provide gate bias voltage and R3 provides a path for DC bias current of M1 to flow to ground 31 Av 1 32 Source Follower Core Source Follower Example vout rO RL 1 vin rO RL gm Av Similar to the emitter follower the source follower can be analyzed as a resistor divider rO1 rO 2 1 rO1 rO 2 g m1 In this example M2 acts as a current source 33 Output Resistance of Source Follower 34 Source Follower with Biasing ID Rout 1 1 rO RL RL gm gm The output impedance of a source follower is relatively low whereas the input impedance is infinite at low frequencies thus a good candidate as a buffer 1 W 2 nCox VDD I D RS VTH 2 L RG sets the gate voltage to VDD whereas RS sets the drain current The quadratic equation above can be solved for ID 35 36 Supply Independent Biasing Example of a CS Stage I 1 rO1 rO 2 rO 3 Av g m1 g m3 1 rO1 rO 2 rO 3 Rout g m3 If Rs is replaced by a current source drain current ID becomes independent of supply voltage 37 Example of a CS Stage II Av 38 Examples of CS and CG Stages rO 2 1 1 rO 3 g m1 g m 3 M1 acts as the input device M3 as the source resistance and M2 as the load M1 acts as the input device and …
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