R. T. HoweEECS 105 Spring 2002 Lecture 23Dept. of EECSUniversity of California, BerkeleyLecture 23• Last time:– Frequency response of voltage and current buffers• Today :– Start multi-stage amplifiersR. T. HoweEECS 105 Spring 2002 Lecture 23Dept. of EECSUniversity of California, BerkeleyMultistage AmplifiersNecessary to meet typical specifications for any of the 4 typesWe have 2 flavors (NMOS, PMOS) of CS, CG, and CDWhat are the constraints?1. Input/output resistance matching2. DC coupling (no passive elements to block the signal)… why not?R. T. HoweEECS 105 Spring 2002 Lecture 23Dept. of EECSUniversity of California, BerkeleyStart: Two-Stage Voltage Amplifier• Use two-port models to explore whether the combination “works”CS1CS2Results: Rin= Rin1, Rout= Rout2, Av=R. T. HoweEECS 105 Spring 2002 Lecture 23Dept. of EECSUniversity of California, BerkeleyUsing CMOS StagesCS1CS2CD3Output resistance: Voltage gain (2-port parameter): Input resistance:R. T. HoweEECS 105 Spring 2002 Lecture 23Dept. of EECSUniversity of California, BerkeleyMultistage Current Buffers CG1CG2 Are two cascaded common-base stages better than one?Input resistance: Rin= Rin1R. T. HoweEECS 105 Spring 2002 Lecture 23Dept. of EECSUniversity of California, BerkeleyCommon-Gate 2ndStage()222022||1ocSmoutoutrRgrRR+≅=R. T. HoweEECS 105 Spring 2002 Lecture 23Dept. of EECSUniversity of California, BerkeleySummary of Cascaded AmplifiersGeneral goals:1. Boost the gain parameter (except for buffers)2. Optimize the input and output resistancesRinRoutVoltage:Current:Transconductance:Transresistance:R. T. HoweEECS 105 Spring 2002 Lecture 23Dept. of EECSUniversity of California, BerkeleySecond Design Issue: DC CouplingConstraint: large inductors and capacitors are not available Output of one stage is directly connected to the inputof the next stage Æ must consider DC levels … why?R. T. HoweEECS 105 Spring 2002 Lecture 23Dept. of EECSUniversity of California, BerkeleyAlternative CG-CC CascadeUse a PMOS CD Stage: DC level shifts upwardR. T. HoweEECS 105 Spring 2002 Lecture 23Dept. of EECSUniversity of California, BerkeleyCG Cascade: DC BiasingTwo stages can have different supply currentsExtreme case:IBIAS2= 0 AR. T. HoweEECS 105 Spring 2002 Lecture 23Dept. of EECSUniversity of California, BerkeleyCG Cascade: Sharing a SupplyFirst stage has no currentsupply of its own Æ its outputresistance is
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