Berkeley ELENG 105 - Lecture 23 (11 pages)

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Lecture 23



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Lecture 23

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Pages:
11
School:
University of California, Berkeley
Course:
Eleng 105 - Microelectronic Devices and Circuits
Microelectronic Devices and Circuits Documents

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EECS 105 Spring 2002 Lecture 23 R T Howe Lecture 23 Last time Frequency response of voltage and current buffers Today Start multi stage amplifiers Dept of EECS University of California Berkeley EECS 105 Spring 2002 Lecture 23 R T Howe Multistage Amplifiers Necessary to meet typical specifications for any of the 4 types We have 2 flavors NMOS PMOS of CS CG and CD What are the constraints 1 Input output resistance matching 2 DC coupling no passive elements to block the signal why not Dept of EECS University of California Berkeley EECS 105 Spring 2002 Lecture 23 R T Howe Start Two Stage Voltage Amplifier Use two port models to explore whether the combination works CS1 CS2 Results Rin Rin1 Rout Rout2 Av Dept of EECS University of California Berkeley EECS 105 Spring 2002 Lecture 23 R T Howe Using CMOS Stages CS1 CS2 CD3 Input resistance Voltage gain 2 port parameter Output resistance Dept of EECS University of California Berkeley EECS 105 Spring 2002 Lecture 23 R T Howe Multistage Current Buffers Are two cascaded common base stages better than one CG1 CG2 Input resistance Rin Rin1 Dept of EECS University of California Berkeley EECS 105 Spring 2002 Lecture 23 R T Howe Common Gate 2nd Stage Rout Rout 2 r02 1 g m 2 RS 2 roc 2 Dept of EECS University of California Berkeley EECS 105 Spring 2002 Lecture 23 R T Howe Summary of Cascaded Amplifiers General goals 1 Boost the gain parameter except for buffers 2 Optimize the input and output resistances Voltage Current Transconductance Transresistance Dept of EECS Rin Rout University of California Berkeley EECS 105 Spring 2002 Lecture 23 R T Howe Second Design Issue DC Coupling Constraint large inductors and capacitors are not available Output of one stage is directly connected to the input of the next stage must consider DC levels why Dept of EECS University of California Berkeley EECS 105 Spring 2002 Lecture 23 R T Howe Alternative CG CC Cascade Use a PMOS CD Stage DC level shifts upward Dept of EECS University of California



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