EE105 Fall 2006 Nathan Pletcher Lab 8 SPICE example In this lab you were to simulate the cascode given in the Lab 8 manual A simplified version of the circuit is shown in Figure 1 with a current source supply instead of the PMOS cascode given in Figure 3 This example will show how to simulate the amplifier in Figure 1 The main difficulty is to figure out how to bias the gate of M1 the input device As shown in the figure the gate is a floating node and SPICE will complain about it The reason is that there is nothing connected to that node to set the voltage On one side is the 10uF cap which has infinite DC resistance On the other side is the gate of M1 which is a capacitor and also has infinite DC resistance Somehow we need to get an appropriate bias voltage on the gate of M1 In this case appropriate means that we set up the gate voltage so that it will be able to have a drain current of Isup which is set by the top current source Remember the simple saturation equation Id W L unCox Vgs Vt 2 We need to give M1 the correct Vgs so that it can have the Id dictated by the current source In the SPICE simulation I will do this by connecting a voltage source to the gate with a resistor I use a huge 1x1015 ohm resistor to make sure that there is no voltage division between the 1Mohm source resistance R1 Alternatively you could use 90kohm because this is the approximate input resistance of the bias network shown in Figure 3 which is what we are trying to emulate But then you will get a voltage division right at the input just like in the lab measurement and that must be taken into account in your calculations For now let s just stick with a 1x1015 ohm resistor and try to simulate the gain of the cascode alone without any input voltage division Next I sweep the bias voltage vvin in my SPICE deck over a narrow range to see when the output voltage is about Vdd 2 That s where I set my DC voltage for vvin I found the approximate solution using the Id equation above and then simply swept SPICE over a narrow range I found that the gate voltage should be 1 19227 for an output voltage of Vdd 2 After setting the DC biasing I can run the op operating point sim and check that the transistors are biased correctly Check out the SPICE output file in this document and note that both MOSFETs are biased in saturation with reasonable terminal voltages With everything biased correctly the last step is to run an AC simulation and check the gain I can t simply divide the DC Vout Vin as some people did in their lab reports because those are just DC voltages The gain is defined as Vout Vin so we have to use an AC sim Looking at the low frequency gain then gives us the gain without the effect of poles and frequency response which is what we want here See the plot at the end of the document The gain is 276 linear scale Does this result make sense Recall that the gain should be Av gm1 Rout But Rout here is very large because of the cascode and the load resistor Rload 250k is in parallel with Rout We can safely assume that the resistance at the output will be dominated by Rload and be approximately 250k Therefore Av gm1 Rload 1 18mS 250k 295 which is only 6 off from the simulated value Not bad huh SPICE deck EE105 lab 8 cascode Nate Pletcher Netlist vvdd vdd 0 dc 3 5 isup vdd vout dc 250u vindc vb 0 dc 1 19227 vbias vg2 0 dc 2 0 vvin vin 0 dc 0 ac 1 c1 vin vx 10u r1 vx vg1 1e6 rb vg1 vb 1e15 c2 vout vy 10u rload vy 0 250k m1 vd1 vg1 0 0 nfet w 46 5u l 1 5u m2 vout vg2 vd1 0 nfet w 46 5u l 1 5u Models model nfet nmos level 1 vto 0 77 kp 86u lambda 0 08 phi 0 74 Options options post nomod Analysis op dc vindc 1 192 1 2 0 00001 ac dec 10 10k 100x end SPICE output file abridged operating point information tnom 25 000 temp 25 000 operating point status is all simulation time is 0 node voltage node voltage node voltage 0 vb 3 5000 0 vg1 0 vout 1 1923 0 vd1 647 3783m 0 vdd 1 1923 1 7576 0 vg2 0 vx 2 0000 1 1923 resistors subckt element 0 r1 0 rb 0 rload r value 1 0000x 1 000e 15 250 0000k v drop 0 120 7193n 0 current 0 1 207e 22 0 power 0 0 0 mosfets subckt element 0 m1 0 m2 model 0 nfet 0 nfet region Saturati Saturati id 250 0000u 250 0000u ibs 0 6 4738f ibd 6 4738f 17 5760f vgs 1 1923 1 3526 vds 647 3783m 1 1102 vbs 0 647 3783m vth 770 0000m 937 5937m vdsat 422 2701m 415 0280m vod 422 2701m 415 0280m beta 2 8041m 2 9028m gam eff 527 6252m 527 6252m gm 1 1841m 1 2047m gds 19 0152u 18 3686u gmb 363 1277u 269 8303u cdtot 20 7902a 35 6540a cgtot 16 3336f 16 2955f cstot 16 0572f 16 0572f cbtot 255 6307a 202 6271a cgs 16 0572f 16 0572f cgd 20 7902a 35 6540a 0 vin 0 vy 0 0
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