12 CMOS Layout Mask Layers IC design procedure Layer system specifications Representation Color Convention EECS 105 circuit design layout n well purple active green select p brown polysilicon red metal blue contact black post layout extraction and simulation IC fabrication testing Layout considerations mask layers devices electrical connectivity interconnect layout design rules EE 105 Fall 1998 Lecture 12 EE 105 Fall 1998 Lecture 12 MOSFET Layout Electrical Connectivity active polysilicon and metal can be used for interconnects wires metal has much lower resistivity than either active or polysilicon metal is separated from active or polysilicon by an insulating oxide a contact is needed for electrical connections between these layers active and polysilicon cannot be connected directly without metal use p doped active select mask as contact to the bulk polysilicon crossing active results in an NMOS device L gate W source drain symmetric PMOS devices are placed in n wells use n doped active no select mask as a contact to n wells select n well contact to bulk EE 105 Fall 1998 Lecture 12 contact to well EE 105 Fall 1998 Lecture 12 Layout Example Layout Rules EECS 105 Technology minimum dimensions and separations in mm not to scale n well polysilicon 4 VDD VDD 1 active metal 2 2 2 A 2 contact 2 1 B 1 6 8 2 10 12 select F 14 16 5 18 20 m 1 2 metal 4 1 contact topoly 2 VSS 3 1 VSS 0 active polysilicon 2 polysilicon active 1 0 2 4 6 8 10 12 14 16 18 20 m n well EE 105 Fall 1998 Lecture 12 EE 105 Fall 1998 Lecture 12 Circuit Extraction Circuit Extraction 1 Find all transistors and sizes 1 Find all transistors and sizes 2 Extract wiring 2 Extract wiring 3 Calculate parasitic capacitance and resistance 3 Calculate parasitic capacitance and resistance F A F B 2 VSS VSS VSS 0 2 4 6 8 10 12 14 16 18 20 m 0 0 VSS 4 4 6 6 8 8 B VDD 10 12 14 16 18 20 m A VDD 0 EE 105 Fall 1998 Lecture 12 2 VDD 10 12 14 16 18 20 m VDD 2 4 6 8 10 12 14 16 18 20 m EE 105 Fall 1998 Lecture 12 Extracted Schematic Circuit Simulation fabricating an IC costs 1000 100 000 per run VDD CA DD 4 5 1 Objectives nice to get it right the first time CB DD check results from hand analysis 4 5 1 A e g validity of assumptions F evaluate functionality speed accuracy of large circuit blocks or entire chips Cw 3 1 B CB SS Simulators SPICE invented at UC Berkeley circa 1970 1975 commercial versions HSPICE PSPICE I SPICE same core as Berkeley SPICE but add functionality improved user interface 3 1 A CA SS EECS 105 student version of PSPICE on PC limited to 10 transistors VSS other simulators for higher speed special needs e g SPLICE RSIM Wire capacitance Cw is found from its capacitance per unit length ox C w W w L w t thox Interconnect capacitances CA SS and CA DD are the sum of polysilicon and metal capacitances to the substrate connected to VSS or the well connected to VDD Could add resistances of polysilicon and metal interconnects EE 105 Fall 1998 Lecture 12 Limitations simulation results provide no insight e g how to increase speed of circuit results sometimes wrong errors in input effect not modeled in SPICE always do hand analysis first and COMPARE RESULTS EE 105 Fall 1998 Lecture 12
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