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Berkeley ELENG 105 - Lecture

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EE 105 Fall 1998Lecture 12CMOS Layout■ IC design procedure:• system specifications• circuit design• layout• post-layout extraction and simulation• IC fabrication• testing■ Layout considerations:• mask layers• devices• electrical connectivity (interconnect)• layout (design) rules12EE 105 Fall 1998Lecture 12Mask LayersLayer RepresentationColor Convention (EECS 105)n-well purpleactive greenselect (p+)brownpolysilicon redmetal bluecontact blackEE 105 Fall 1998Lecture 12MOSFET Layout■polysilicon crossing active results in an NMOS device:■ PMOS devices are placed in n-wells:LWgatesource / drain (symmetric)n-wellselectEE 105 Fall 1998Lecture 12Electrical Connectivity■active, polysilicon, and metal can be used for interconnects (wires)■metal has much lower resistivity than either active or polysilicon■metal is separated from active or polysilicon by an (insulating) oxide; a contact is needed for electrical connections between these layers■active and polysilicon cannot be connected directly (without metal)■ use p-doped active (select mask) as contact to the bulkuse n-doped active (no select mask) as a contact to n-wellscontact to bulkcontact to wellEE 105 Fall 1998Lecture 12Layout Rules (EECS 105 Technology)minimum dimensions and separations (in mm, not to scale):active22contact11n-well45polysilicon11select22metal22n-wellpolysiliconactive112321metalactivepolysiliconcontact-to-polyEE 105 Fall 1998Lecture 12Layout ExampleABFVDDVSSVDDVSS0 2 4 6 8 10 12 14 16 18 20µm0 2 4 6 8 10 12 14 16 18 20µmEE 105 Fall 1998Lecture 12Circuit Extraction1) Find all transistors and sizes2) Extract wiring 3) Calculate (parasitic) capacitance and resistanceABFVDDVSSVDDVSS0 2 4 6 8 101214161820µm0 2 4 6 8 10 12 14 16 18 20µmEE 105 Fall 1998Lecture 12Circuit Extraction1) Find all transistors and sizes2) Extract wiring 3) Calculate (parasitic) capacitance and resistanceABFVDDVSSVDDVSS0 2 4 6 8 101214161820µm0 2 4 6 8 10 12 14 16 18 20µmEE 105 Fall 1998Lecture 12Extracted Schematic■ Wire capacitance Cw is found from its capacitance per unit length --■ Interconnect capacitances CA-SS and CA-DD are the sum of polysilicon and metal capacitances to the substrate (connected to VSS ) or the well (connected to VDD)■ Could add resistances of polysilicon and metal interconnectsA A BVSSVDDF(3/1)(3/1)(4.5/1)(4.5/1)CwCA-SSCA-DDCB-SSCB-DDCwεoxtthox-----------WwLw=EE 105 Fall 1998Lecture 12Circuit Simulation■Objectives:• fabricating an IC costs $1000 ... $100,000 per run---> nice to get it “right” the first time• check results from hand-analysis(e.g. validity of assumptions)• evaluate functionality, speed, accuracy, ... of large circuit blocks or entire chips■Simulators:• SPICE: invented at UC Berkeley circa 1970-1975commercial versions: HSPICE, PSPICE, I-SPICE, ... (same core as Berkeley SPICE, but add functionality, improved user interface, ...)EECS 105: student version of PSPICE on PC, limited to 10 transistors• other simulators for higher speed, special needs (e.g. SPLICE, RSIM)■Limitations:• simulation results provide no insight (e.g. how to increase speed of circuit)• results sometimes wrong (errors in input, effect not modeled in SPICE)===> always do hand-analysis first and COMPARE


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Berkeley ELENG 105 - Lecture

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