Experiment 6 Gated Lateral BJT Characteristics W T Yeung W Y Leung S Pimputkar J W P Chen W Belachew and R T Howe UC Berkeley EE 105 Fall 2003 Contents 1 Objective 2 Gated Lateral BJT Usage 2 1 Layout and Cross Section 2 2 Effect of the Gate Surface vs Subsurface Current 2 3 Effect of the Substrate Current Splitting 2 4 Effect of Doping Levels 1 2 2 4 5 5 3 Prelab 5 4 Ebers Moll Model Parameter Extraction 4 1 Parameter Extraction Using the HP 4155 4 1 1 Extraction of F R VAF VAR 4 1 2 Extraction of IS 4 2 Parameter Extraction and Regions of Operation Using Circuit Measurements 6 7 7 8 9 5 Optional Experiments 12 5 1 Circuit Simulation Basic 12 1 Objective In this lab you will characterize a gated lateral BJT After a brief introduction to gated lateral BJT s and how they differ from conventional pnp BJT s you will measure all the parameters needed to model the device using the full Ebers Moll pnp BJT model a largesignal model This will be done both using the HP 4155 and more basic equipment Next 1 of 12 Gated Lateral BJT Usage FIGURE 1 Circuit Symbol for a the gated lateral BJT and b the canonical pnp BJT E E G B B C VSS a C b for each region of operation you will observe how the BJT operates and derive the corresponding simplified Ebers Moll circuit model Optionally you will use the collected data to write a SPICE model for the BJT and use it run sample simulations The key concepts introduced in this laboratory are Determination of the Ebers Moll large signal parameters VA and IS The four regions of operation of the BJT Determination of the region of operation from the voltages VEB and VCB 2 Gated Lateral BJT Usage In this lab you will not be using a using a conventional BJT but rather a gated lateral BJT you will need to be aware of the differences between the two to do the lab As you know the vast majority of modern microchips including the EE105 lab chip are manufactured in CMOS processes which do not accomodate for bipolar transistors Nevertheless under certain bias conditions several second order effects in the p MOSFET become dominant and the pnp sandwich formed by source n well and drain acts like a pnp BJT perturbed by nonidealities introduced by the gate and substrate which contact the pnp sandwich This device is called a gated lateral BJT or more commonly lateral BJT if it is clear one is refering to a CMOS process and is given the circuit symbol shown in Fig 1 a the symbol for a canonical BJT as covered in lecture is shown in Fig 1 b for comparison 2 1 Layout and Cross Section To better understand the structure consider the gated lateral BJT layout and cross section shown in Fig 2 Most of the structure is needed simply to contact the various regions At the center of the layout is a p MOSFET whose gate has been fingered for compactness following common MOSFET layout practice The four diffusion regions are alternately part of the source and drain which will now serve as the emitter and collector respectively Two small strips of layer 1 metal connect to the two source diffusion regions via three contacts apiece a fork shaped layer 2 metal wire labeled E then connects to both metal 1 strips through a via each A similar structure is used for the collector labeled C As indicated by the circuit symbols in the cross section the heart of the BJT is the pnp sandwich of MOSFET source diffusion n well and drain diffusion The n well serves as the base and is Ohmically contacted by the base wire through a ring like n diffusion Experiment 6 Gated Lateral BJT Characteristics 2 of 12 Gated Lateral BJT Usage FIGURE 2 Gated Lateral BJT Layout and Cross Section E G B C Thin Oxide N Well Contact Via Metal 1 Metal 2 p n p n B p VSS p E VSS Poly E p C p E G C p C B n VSS p p gated lateral BJT Experiment 6 Gated Lateral BJT Characteristics parasitic vertical BJT 3 of 12 Gated Lateral BJT Usage FIGURE 3 MOSFET Cross Section with Indicated Paths for Potential Plots X S G Y Y X FIGURE 4 D B Potential Plots along Path XX in Fig 3 for a zero emitter junction bias VEB 0 and b forward emitter junction bias VEB 0 x accumulation x flatband VEB x 0 x 0 depletion gate p oxide base n gate p oxide a base n b surrounding the MOSFET in the layout As seen in the cross section the substrate contacts the n well as well and represents a second parasitic collector labelled VSS It is necessary to draw off the emitter current extracted by the substrate lest it disturb the surrounding circuitry or even trigger latchup a destructive situtation in which the junctions of parasitic pnpn sandwichs are locked into forward bias Similar to the n well base the substrate is contacted by a ring shaped diffusion surrounding the n well called a guard ring since it serves to guard against latchup 2 2 Effect of the Gate Surface vs Subsurface Current The effect of the gate can be completely eliminated by biasing the MOS structue at flatband or in accumulation VGB VFB This is best understood by considering the potential curves for the MOS structure shown in Fig 4 a for the case VEB VSB 0 and in Fig 4 b for the case VEB VSB 0 At flatband and in accumulation the potential level is flat throughout the base If there were no gate at all this uniform potential would be interpreted as steming from a uniform base doping which is assumed in the 1 dimensional BJT model covered in lecture In depletion the gate bends down the potential curves in the base near the silicon surface corresponding to reduced base doping at the surface While this low effective base doping can be used to advantage to produce BJT s with extremely high values of common emitter current gain beyond 106 nonuniform base doping is not covered by the 1 dimensional model you covered in lecture and therefore it will be easier for us to build a BJT with equivalently uniform base doping by biasing VGB VFB and then just ignore the gate completely Experiment 6 Gated Lateral BJT Characteristics 4 of 12 Prelab 2 3 Effect of the Substrate Current Splitting As pointed out in the discussion of the cross section the substrate forms a parasitic second collector which collects about 30 of the emitter current an effect called current splitting Unlike with the gate this effect cannot be eliminated at least not with the gate bias we will be using Our approach will be to ignore the substrate current ISS with the following caveats The collector current IC is now too low by the amount ISS in forward active region In …
View Full Document
Unlocking...