Berkeley ELENG 105 - Gated Lateral BJT Characteristics (12 pages)

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Gated Lateral BJT Characteristics



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Gated Lateral BJT Characteristics

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Pages:
12
School:
University of California, Berkeley
Course:
Eleng 105 - Microelectronic Devices and Circuits
Microelectronic Devices and Circuits Documents

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Experiment 6 Gated Lateral BJT Characteristics W T Yeung W Y Leung S Pimputkar J W P Chen W Belachew and R T Howe UC Berkeley EE 105 Fall 2003 Contents 1 Objective 2 Gated Lateral BJT Usage 2 1 Layout and Cross Section 2 2 Effect of the Gate Surface vs Subsurface Current 2 3 Effect of the Substrate Current Splitting 2 4 Effect of Doping Levels 1 2 2 4 5 5 3 Prelab 5 4 Ebers Moll Model Parameter Extraction 4 1 Parameter Extraction Using the HP 4155 4 1 1 Extraction of F R VAF VAR 4 1 2 Extraction of IS 4 2 Parameter Extraction and Regions of Operation Using Circuit Measurements 6 7 7 8 9 5 Optional Experiments 12 5 1 Circuit Simulation Basic 12 1 Objective In this lab you will characterize a gated lateral BJT After a brief introduction to gated lateral BJT s and how they differ from conventional pnp BJT s you will measure all the parameters needed to model the device using the full Ebers Moll pnp BJT model a largesignal model This will be done both using the HP 4155 and more basic equipment Next 1 of 12 Gated Lateral BJT Usage FIGURE 1 Circuit Symbol for a the gated lateral BJT and b the canonical pnp BJT E E G B B C VSS a C b for each region of operation you will observe how the BJT operates and derive the corresponding simplified Ebers Moll circuit model Optionally you will use the collected data to write a SPICE model for the BJT and use it run sample simulations The key concepts introduced in this laboratory are Determination of the Ebers Moll large signal parameters VA and IS The four regions of operation of the BJT Determination of the region of operation from the voltages VEB and VCB 2 Gated Lateral BJT Usage In this lab you will not be using a using a conventional BJT but rather a gated lateral BJT you will need to be aware of the differences between the two to do the lab As you know the vast majority of modern microchips including the EE105 lab chip are manufactured in CMOS processes which do not accomodate for bipolar transistors Nevertheless under certain



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