EECS 105 Spring 2004 Lecture 34 Lecture 34 Designing amplifiers biasing frequency response Prof J S Smith Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 34 Prof J S Smith Context We will figure out more of the design parameters for the amplifier we looked at in the last lecture and then we will do a review of the approximate frequency analysis of circuits which have a single dominant pole Department of EECS University of California Berkeley 1 EECS 105 Spring 2004 Lecture 34 Prof J S Smith Reading z Chapter 9 multi stage amplifiers The frequency analysis is in the first section of chapter 10 but we won t go farther into chapter 10 for a while z The Lectures on Wednesday and Friday will be given by Joe and Jason respectively They will be doing several example problems Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 34 Prof J S Smith Lecture Outline z z z Department of EECS Example 1 Cascode Amp Design Example 2 CS NMOS CS PMOS Review of frequency analysis with a dominant pole University of California Berkeley 2 EECS 105 Spring 2004 Lecture 34 Prof J S Smith Amplifier Schematic Note that the backgate connection for M2 is not specified ignore gmb Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 34 Prof J S Smith Complete Amplifier Schematic Bias voltages derived from transistors under similar operating conditions to the transistors they supply Goals gm1 1 mS Rout 10 M Cascode current source For high roc CG output CS input with low voltage gain Department of EECS University of California Berkeley 3 EECS 105 Spring 2004 Lecture 34 Prof J S Smith Current Supply Design High impedance current source means all of the small signal current goes to the load resistance giving more SS voltage gain Output resistance goal requires large roc for high gain so we used a cascode current source Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 34 Prof J S Smith Totem Pole Voltage Supply DC voltages must be set for the cascode current supply transistors M3 and M4 as well as the gate of M 2 M2B supplies the Bias quiescent voltage For the CG stage Department of EECS University of California Berkeley 4 EECS 105 Spring 2004 Lecture 34 Prof J S Smith Miller Capacitance of Input Stage Find the Miller capacitance for Cgd1 C gd Input resistance to common gate second stage is low gain across Cgd1 is small Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 34 Prof J S Smith Two Port Model with Capacitors Miller capacitance C M 1 AvC gd 1 C gd 1 AvCdg 1 Department of EECS g m1 gm2 University of California Berkeley 5 EECS 105 Spring 2004 Lecture 34 Prof J S Smith Schematic Goals gm1 1 mS Rout 10 M Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 34 Prof J S Smith Device Sizes M1 select W L 1 200 2 to meet specified gm1 1 mS find VBIAS 1 2 V Cascode current supply devices select VSG 1 5 V W L 4 W L 4B W L 3 W L 3B 64 2 Department of EECS University of California Berkeley 6 EECS 105 Spring 2004 Lecture 34 Prof J S Smith Device Sizes M2 select W L 2 50 2 to meet specified Rout 10 M find VGS2 1 4 V Match M2 with diode connected device M2B Assuming perfect matching and zero input voltage what is VOUT Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 34 Prof J S Smith Output Voltage Swing Maximum VOUT Minimum VOUT Department of EECS University of California Berkeley 7 EECS 105 Spring 2004 Lecture 34 Prof J S Smith Two Port Model Find output resistance Rout n 1 20 V 1 n 1 50 V 1 at L 2 m ron 100 A 20 V 1 1 200 k rop 500 k 2I D2 2 100 A 500 S VGS 2 VTn 1 4V 1V 2 I D 3 2 100 A 400 S VSG 3 VTp 1 5V 1V gm2 g m3 Rout roc ro 2 1 g m 2 RS 2 ro 3 1 g m 3 RS 3 ro 2 1 g m 2 ro1 Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 34 Prof J S Smith Voltage Transfer Curve Open circuit voltage gain Av vout vin gm1Rout 103 10 7 vOUT 4 dvout dvin Q 10 000 3 2 1 0 Department of EECS 1 2 3 4 vIN University of California Berkeley 8 EECS 105 Spring 2004 Lecture 34 Prof J S Smith Multistage Amplifier Design Example Start with basic two stage transconductance amplifier Why do this combination Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 34 Prof J S Smith Quiescent level shifts NMOS PMOS CS typical typical CG CD known shift known shift Source follower Department of EECS University of California Berkeley 9 EECS 105 Spring 2004 Lecture 34 Prof J S Smith CS CS Amplifier Direct DC connection use NMOS then PMOS Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 34 Prof J S Smith Current Supply Design Assume that the reference is a sink set by a resistor Must mirror the reference current and generate a sink for iSUP 2 Department of EECS University of California Berkeley 10 EECS 105 Spring 2004 Lecture 34 Prof J S Smith Use Basic Current Supplies Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 34 Prof J S Smith Complete Amplifier Topology What s missing The device dimensions the bias voltage and reference resistor Department of EECS University of California Berkeley 11 EECS 105 Spring 2004 Lecture 34 Prof J S Smith DC Bias Find Operating Points Find VBIAS such that VOUT 0 V Device parameters nCox 50 A V2 p Cox 25 A V2 VTn 1 V VTp 1 V n 0 05 V 1 p 0 05 V 1 Device dimensions for lecture design W L n 50 2 W L p 80 2 Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 34 Prof J S Smith Finding RREF V Require IREF ID3 50 A M3 VSG 3 VTp RREF VSG 3 1 V V I REF 50 A 50 A Department of EECS 2I D3 p Cox W L 3 2 50 A 4 1 1 32V 25 A 80 2 40 V VSG 3 V Rref 2 5 1 32 2 5 R Rref ref 74k University of California Berkeley 12 EECS 105 Spring 2004 Lecture 34 Prof J S Smith DC Operating Point IREF 50 A VBIAS VGS 1 Vtn 2 I D1 nCox W L 1 100 A 9 V 50 A V 2 50 2 7 Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 34 Prof J S Smith Small Signal Device Parameters Transistors M1 and M2 ro1 400 k gm1 350 S …
View Full Document
Unlocking...