EECS 105 Spring 2004 Lecture 16 EECS 105 Spring 2004 Lecture 16 Prof J S Smith Reading Lecture 16 MOS Transistor models Linear models SPICE models z z z Prof J S Smith Department of EECS z We are next going to look at the analog characteristics of simple digital devices 5 2 5 4 And following the midterm we will cover PN diodes again in forward bias and develop small signal models Chapter 6 we will then take a week on bipolar junction transistor BJT Chapter 7 Then go on to design of transistor amplifiers chapter 8 University of California Berkeley Department of EECS University of California Berkeley Prof J S Smith EECS 105 Spring 2004 Lecture 16 Prof J S Smith EECS 105 Spring 2004 Lecture 16 Context Transistor equations Cutoff In the last lecture we discussed the MOS transistor and z added a correction due to the changing depletion region called the body effect Did a review of small signal models Started small signal models for the FET VGS VTP ID 0 Linear We discussed a physical model for these parameters but often they will be used to fit the observed curves for a given manufacturing process VGS VTN VDS VGS VTN W VGS VT VDS 12 VDS2 I D Cox VGS VTP VDS VGS VTP L Saturation In this lecture we will Department of EECS VGS VTN Continue to build the small signal models for MOS FETs look at how MOS Transistors are modeled in SPICE VGS VTN VDS VGS VTN VGS VTP VDS VGS VTP I D 12 Cox W VGS VT 2 1 VDS L Note if VSB 0 need to calculate VT University of California Berkeley Department of EECS University of California Berkeley 1 EECS 105 Spring 2004 Lecture 16 Prof J S Smith EECS 105 Spring 2004 Lecture 16 Circuit models z Prof J S Smith Large signal models We are now going to produce circuit models which will translate the mathematics into drawings of circuit elements so that we can design real circuits using our developed intuition z Large signal models try to recreate the behavior of real devices over large voltage swings may not be linear and may not be terribly accurate in the details For example a PN junction might be modeled as a perfect diode which always blocks current in the forward direction and passes current with no voltage drop in the reverse direction Department of EECS University of California Berkeley Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 16 Prof J S Smith EECS 105 Spring 2004 Lecture 16 Prof J S Smith Circuit models z DC Large signal model for a FET In order to translate mathmatical expressions into an equivalent circuit we will use resistors capacitors and variable current sources hooking them up with perfect wires Perfect wires have no parasitic capacitance or inductance and convert into equations by Kirchoff s laws i t v t C R i2 gv1 ID VGS VSB v1 Sometimes a circuit model is very close to mathematics for example We can directly convert our mathematical model for the FET into VSD Where VGT 0 0 2 ID W Vmin k L VGT Vmin 2 1 VDS VGT 0 Vmin min VGT VDS Vsat VGT VGS VT and VT VT 0 2 f VSB 2 f Department of EECS University of California Berkeley Department of EECS University of California Berkeley 2 EECS 105 Spring 2004 Lecture 16 Prof J S Smith EECS 105 Spring 2004 Lecture 16 Typical parameters z Simplified large signal model Here are some parameters for an actual 0 25 micron process Volts VT 0 Root volts volts VDSAT A V2 k Prof J S Smith z volts 1 To think about and design circuits we will often use rough models which behave somewhat like the physical device under a particular circumstance For example we might model a FET as a resistive switch D G NMOS 0 43 0 4 0 63 115 10 6 0 06 PMOS 0 4 0 4 1 30 10 6 0 1 VGS C VDS R Where C and R are chosen purely to give us an approximation to the observed value under the operating conditions S Department of EECS University of California Berkeley Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 16 Prof J S Smith EECS 105 Spring 2004 Lecture 16 Prof J S Smith Limitations of large signal models z z z Large signal models must often be greatly simplified to handle intuitively Large signal models are often nonlinear so it is difficult to analyze circuits with more than a few elements directly Elements such as variable stored charge are difficult to model often use a fixed capacitance which has a compromise value Department of EECS University of California Berkeley Small signal models z z If we linearize the model as discussed in the last lecture by picking an operating point and allowing only small signal variations around those operating points for both voltages and currents we can produce a small signal model one which includes only linear elements This will let use linear circuit theory which is a way we can handle very large numbers of interacting components Department of EECS University of California Berkeley 3 EECS 105 Spring 2004 Lecture 16 Prof J S Smith EECS 105 Spring 2004 Lecture 16 Prof J S Smith Backgate Transconductance Small signal model for the MOS FET The current from the drain of our FET can be modeled for small signals VT VT 0 iDS t I DS ids VSB 2 p 2 p For a given operating point voltage for Vgs and Vds we get ids Which we will then label iDS i vgs DS vds vgs vds ids g m vgs Transconductance 1 vds ro Conductance Result g mb iD vBS Q iD VTn Q VTn vBS Q gm 2 VBS 2 p Department of EECS University of California Berkeley Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 16 Prof J S Smith EECS 105 Spring 2004 Lecture 16 Prof J S Smith Substrate potential Transconductance z Let s look at the back gate effect in a small signal model Effect changes threshold voltage which changes the drain current substrate acts like a backgate g mb Department of EECS i D vBS VGS VDS VBS i D vBS Notice that we have terms in our equations which give the small signal current into one terminal in as a constant times the small signal voltage into another terminal In order to translate that into a linear equivalent circuit we will use a variable current source but where the current is just proportional to a voltage v1 are all held constant University of California Berkeley i2 gv1 Where g is called the transconductance Department of EECS University of California Berkeley 4 EECS 105 Spring 2004 Lecture 16 Prof J S Smith Combining terms Small Signal Model We now have three small signal contributions to the current into the drain terminal for our FET from changes in Vgs Vbs and Vds ids g m vgs g mb vbs …
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