Announcements Homework 5 due next Tuesday EE105 Fall 2005 Lab 3 this week Lab 4 next week Microelectronic Devices and Circuits Reading Chapter 4 4 5 4 6 8 3 Midterm 1 in two weeks Lecture 10 October 13 6 30 8pm Sibley MOS Transistor Small Signal Model 2 Lecture Material Large Signal Analysis Last lecture Sample and hold MOS amplifier example vO vDS VDD This lecture MOSFET small signal model 0 t vIN vGS t 3 4 An MOS Amplifier There is a Better Way What s missing didn t include device output impedance or charge storage effects must solve nonlinear differential equations Approach 2 Do problem in two steps Input signal RD VDD Supply Rail vo DC voltages and currents ignore small signals sources set bias point of the MOSFET we had to do this to pick VGS already Substitute the small signal model of the MOSFET and the smallsignal models of the other circuit elements vs vGS VGS vs VGS I DS Output signal This constitutes small signal analysis 5 6 1 Step 2 Small Signal Modeling Small Signal Analysis Step 1 Find DC Bias ignore small signal source IDS Q What are the small signal models of the DC supplies VGS was found in Lecture 9 7 Small Signal Models of Ideal Supplies The Transconductance gm Small signal model isupply gsupply vsupply rsupply 0 gsupply vsupply Defined as the change in drain current due to a change in the gatesource voltage with everything else constant I DS sat gm short isupply 8 iD vGS W Cox VGS VT 2 1 VDS L 2 VGS VDS Cox VGS VDS g m Cox 0 g m Cox rsupply open iD vGS W L W VGS VT L Gate Bias 2 I DS W 2 Cox I DS W L Cox L gm 9 0 W VGS VT 1 VDS L 2 I DS VGS VT Drain Current Bias Drain Current Bias and Gate Bias 10 Evaluating ro Output Resistance ro Defined as the inverse of the change in drain current due to a change in the drain source voltage with everything else constant iD W Cox VGS VT 2 1 VDS L 2 i ro D vDS Non Zero Slope I DS r0 VDS 1 1 W Cox VGS VT 2 L 2 r0 11 VGS VDS 1 I DS 12 2 Putting Together a Circuit Model Total Small Signal Current iDS t I DS ids ids iDS i vgs DS vds vgs vds ids g m vgs Transconductance 1 vds ro ids g m vgs Conductance 1 vds ro 13 MOS Amplifier MOS Amplifier Small Signal VDD RD vo vgs vs 1 DC solution ID 0 1mA VGS 1 32V VDS 2 5V id gmvgs vo idRd ro gmvsRd 2 Small signal I DS vs 14 gm VGS ro v AV o g m Rd vs 2IDS 0 625mA V VGS VTn Av 15 6 1 IDS 15 MOS Amplifier 16 Input and Output Waveforms Output resistance typical value 0 05 V 1 ro Voltage gain 1 200k IDS Output small signal voltage amplitude 14 x 25 mV 350 2 0 1 Av 25 200 14 3 0 32 Input small signal voltage amplitude 25 mV Output resistance lowers voltage gain 17 18 3 What Limits the Output Amplitude Role of the Substrate Potential 1 vOUT t reaches VDD or 0 or Need not be the source potential but VB VS Lower substrate potential increased voltage across depletion region increased bulk charge 2 MOSFET leaves constant current region and enters triode region vo max VDD VDD Effect changes threshold voltage which changes the drain current substrate acts like a backgate vo min VDS SAT VGS VTn 0 32V Vo max VDD VGS VTn 2 18V VT VT 0 VSB 2 p 2 p Optimum bias point Vo 0 vIN 19 Role of the Substrate Potential 20 Four Terminal Small Signal Model Effect Modulates threshold acts as a weak backgate g mb iD v BS Q iD v BS Q Q VGS VDS VBS Result g mb iD vBS Q iD VTn Q VTn vBS Q ids g m vgs g mb vbs gm 2 VBS 2 p 1 vds ro 21 22 Gate Source Capacitance Cgs MOSFET Capacitances in Saturation Gate source capacitance channel charge is not controlled by drain in saturation Wedge shaped charge in saturation effective area is 2 3 WL see H S 4 5 4 for details C gs 2 3 WLCox Cov Overlap capacitance along source edge of gate Cov LDWCox Underestimate due to fringing fields 23 24 4 Junction Capacitances Gate Drain Capacitance Cgd Drain and source diffusions have different junction capacitances since VSB and VDB VSB VDS aren t the same Not due to change in inversion charge in channel Overlap capacitance Cov between drain and source is Cgd Complete model without interconnects 25 26 Square Law PMOS Characteristics P Channel MOSFET Measurement of IDp versus VSD with VSG as a parameter 27 28 MOSFET SPICE Model Small Signal PMOS Model Many levels we will use the square law Level 1 model See H S 4 6 Spice refs on reserve for details 29 30 5
View Full Document
Unlocking...