1EE105 - Fall 2005Microelectronic Devices and CircuitsLecture 10MOS TransistorSmall-Signal Model2AnnouncementsHomework 5 due next TuesdayLab 3 this week, Lab 4 next weekReading: Chapter 4 (4.5-4.6), 8.3Midterm 1 in two weeksOctober 13, 6:30-8pm, Sibley3Lecture MaterialLast lectureSample and holdMOS amplifier exampleThis lectureMOSFET small-signal model4Large-Signal AnalysisVDDvIN= vGS0vO= vDStt5There is a Better Way!What’s missing: didn’t include device output impedance or charge storage effects (must solve non-linear differential equations…)Approach 2. Do problem in two steps.DC voltages and currents (ignore small signals sources): set bias point of the MOSFET ... we had to do this to pick VGSalreadySubstitute the small-signal model of the MOSFET and the small-signal models of the other circuit elements …This constitutes small-signal analysis6An MOS AmplifierDSIGSVsvDRDDVGS GS svVv=+ovInput signalOutput signalSupply “Rail”27Small-Signal AnalysisStep 1. Find DC Bias – ignore small-signal sourceVGSwas found inLecture 9IDS,Q8Step 2: Small-Signal ModelingWhat are the small-signal models of the DC supplies?9Small-Signal Models of Ideal SuppliesSmall-signal model:supplysupplysupplyigv∂==∞∂supply0r=supplysupplysupply0igv∂==∂supplyr=∞shortopen10The Transconductance gmDefined as the change in drain current due to a change in the gate-source voltage, with everything else constant,,()(1)GS DS GS DSDDmoxGSTDSGS GSVV VVii WgCVV Vvv Lµλ∆∂=== −+∆∂2,()(1)2oxDSsat GS T DSCWIVV VLµλ=−+()moxGSTWgCVVLµ=−0≈22DSmox oxDSoxIWWgCCIWLLCLµµµ==2()DSmGS TIgVV=−Gate BiasDrain Current BiasDrain Current Bias and Gate Bias11Output Resistance roDefined as the inverse of the change in drain current due to a change in the drain-source voltage, with everything else constantNon-Zero SlopeDSVδDSIδ12Evaluating ro1,GS DSDoDSVVirv−⎛⎞∂⎜⎟=⎜⎟∂⎝⎠2()(1)2oxDGS T DSCWiVVVLµλ=−+021()2oxGS TrCWVVLµλ=−01DSrIλ≈313Total Small Signal Current()DSDSdsit I i=+DS DSds gs dsgs dsiiivvvv∂∂=+∂∂1ds m gs dsoigv vr=+TransconductanceConductance14Putting Together a Circuit Model1ds m gs dsoigv vr=+15MOS AmplifierDSIGSVsvDRDDVov1: DC solutionID= 0.1mAVGS= 1.32V, VDS= 2.5V2: Small signalmA/V625.02=−=TnGSDSmVVIg∞→λ=DSoIr116MOS Amplifier: Small-Signalvgs= vsid= gmvgsvo= - idRd||ro= - gmvsRdAv= -15.6dmsoVRgvvA −==17MOS AmplifierOutput resistance: typical value λ = 0.05 V-1Voltage gain:()20.125|| 200 14.30.32vA⋅⎛⎞=− =−⎜⎟⎝⎠Ω=λ= kIrDSo2001Output resistance lowers voltage gain18Input and Output WaveformsOutput small-signal voltage amplitude: 14 x 25 mV = 350Input small-signal voltage amplitude: 25 mV419What Limits the Output Amplitude?1. vOUT(t) reaches VDDor 0… or 2. MOSFET leaves constant-current region and enterstriode regionVDDvIN0vo,max= VDDvo,min= VDS, SAT= VGS–VTn= 0.32VVo,max= VDD–(VGS– VTn) = 2.18VOptimum bias point Vo = 20Role of the Substrate PotentialNeed not be the source potential, but VB< VSLower substrate potential, increased voltage across depletion region – increased bulk chargeEffect: changes threshold voltage, which changes the drain current … substrate acts like a “backgate”()022TT SB p pVV Vγφφ=+ − −−21Role of the Substrate PotentialEffect: Modulates threshold (acts as a weak “backgate”)QBSDQBSDmbvivig∂∂=∆∆=Q = (VGS, VDS, VBS)Result:22Tn mDDmbBS Tn BSBSpQQQVgiigvVvVγφ∂∂∂== =∂∂∂−−22Four-Terminal Small-Signal Model1ds m gs mb bs dsoigvgv vr=+ +23MOSFET Capacitances in SaturationGate-source capacitance: channel charge is not controlled by drain in saturation.24Gate-Source Capacitance CgsWedge-shaped charge in saturation Æ effective area is (2/3)WL(see H&S 4.5.4 for details)ovoxgsCWLCC+=)3/2(Overlap capacitance along source edge of gate ÆoxDovWCLC=(Underestimate due to fringing fields)525Gate-Drain Capacitance CgdNot due to change in inversion charge in channelOverlap capacitance Covbetween drain and sourceis Cgd26Junction CapacitancesDrain and source diffusions have (different) junctioncapacitances since VSBand VDB= VSB+ VDSaren’t the sameComplete model (without interconnects)27P-Channel MOSFETMeasurement of –IDpversus VSD, with VSGas a parameter:28Square-Law PMOS Characteristics29Small-Signal PMOS Model30MOSFET SPICE ModelMany “levels” … we will use the square-law “Level 1” modelSee H&S 4.6 + Spice refs. on reserve for
View Full Document
Unlocking...