4 29 2008 Lecture 23 Cascode Differential Pair Rout 1 g m 3 rO1 r 3 rO 3 rO1 r 3 OUTLINE BJT Differential Amplifiers cont d Rout g m 3 rO1 r 3 rO 3 rO1 r 3 Cascode differential amplifiers Common mode rejection Differential pair with active load Half circuit for ac analysis Reading Chapter 10 4 10 6 1 Av gm1Rout gm1 gm3 rO1 r 3 rO3 rO1 r 3 EE105 Spring 2008 Lecture 23 Slide 1 Prof Wu UC Berkeley EE105 Spring 2008 Lecture 23 Slide 2 Prof Wu UC Berkeley Example Telescopic Cascode Differential Pair R R Rop 1 g m 5 rO 7 r 5 1 rO 5 rO 7 r 5 1 2 2 Av g m1 g m 3 rO 3 rO1 r 3 Rop Half circuit for ac analysis Half circuit for ac analysis Av g m1 g m3 rO 3 rO1 r 3 g m5 rO 5 rO 7 r 5 EE105 Spring 2008 EE105 Fall 2007 Lecture 23 Slide 3 Prof Wu UC Berkeley EE105 Spring 2008 Lecture 23 Slide 4 Prof Wu UC Berkeley 1 4 29 2008 Effect of Input CM Noise Effect of Finite Tail Impedance If the tail current source is not ideal then when an input common mode voltage is applied the currents in Q1 and Q2 and hence the output common mode voltage will change Vout CM Vin CM EE105 Spring 2008 RC 2 RC 1 1 REE 2 REE 2gm gm Ideal Tail Current There is no effect of the input CM noise at the output Common mode gain should be small Lecture 23 Slide 5 Prof Wu UC Berkeley EE105 Spring 2008 Effect of Input CM Noise The single ended outputs are corrupted by the input CM noise VP REE Prof Wu UC Berkeley Comparison Non Ideal Tail Current ITAIL I EE Lecture 23 Slide 6 Ideal Tail Current ITAIL 2 Non Ideal Tail Current The differential output voltage signal is the same for both cases cases For small input CM noise the differential pair is not affected ITAIL Tail current ITAIL now changes with VP and VP is affected by VCM EE105 Spring 2008 EE105 Fall 2007 Lecture 23 Slide 7 Prof Wu UC Berkeley EE105 Spring 2008 Lecture 23 Slide 8 Prof Wu UC Berkeley 2 4 29 2008 CM to DM Conversion gain ACM DM Example If finite tail impedance and asymmetry e g in load resistance are both present then the differential output signal will contain a portion of the input common mode signal VCM VBE 2 I C REE I C VCM 1 2 REE gm I C 2 I C REE gm I C I C Vout1 I C RC Vout 2 I C RC RC Vout Vout1 Vout 2 I C RC ACM DM Vout RC VCM 1 g m 2 REE EE105 Spring 2008 Lecture 23 Slide 9 Prof Wu UC Berkeley EE105 Spring 2008 R C 1 2 1 g m 3 R1 r 3 rO 3 R1 r 3 g m1 Lecture 23 Slide 10 Prof Wu UC Berkeley Common Mode Rejection Ratio Differential to Single Ended Conversion CMRR is the ratio of the wanted amplified differential input signal to the unwanted converted input common mode noise that appears at the output Many circuits require a differential to single ended conversion CMRR ADM ACM DM This topology is not very good its most critical drawback is supply noise corruption since no common mode cancellation mechanism exists Also we lose half of the voltage signal EE105 Spring 2008 EE105 Fall 2007 Lecture 23 Slide 11 Prof Wu UC Berkeley EE105 Spring 2008 Lecture 23 Slide 12 Prof Wu UC Berkeley 3 4 29 2008 A Better Alternative Active Load This circuit topology performs differential to single ended conversion with no loss of gain vout g m ro NPN ro PNP vin1 vin 2 EE105 Spring 2008 Lecture 23 Slide 13 Prof Wu UC Berkeley Differential Pair with Active Load The input differential pair decreases the current drawn from RL by I and the active load pushes an extra I into RL by current mirror action these effects enhance each other EE105 Spring 2008 EE105 Fall 2007 Lecture 23 Slide 15 Prof Wu UC Berkeley With a current mirror as the load the signal current produced by Q1 can be replicated onto Q4 This type of load is different from the conventional static load and is called an active load EE105 Spring 2008 Lecture 23 Slide 14 Prof Wu UC Berkeley Active Load vs Static Load The load in the circuit on the left responds to the input signal and enhances the single ended output whereas the load in the circuit on the right does not EE105 Spring 2008 Lecture 23 Slide 16 Prof Wu UC Berkeley 4
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