4/29/2008EE105 Fall 2007 1Lecture 23OUTLINE• BJT Differential Amplifiers (cont’d)– Cascode differential amplifiers– Common‐mode rejection– Differential pair with active loadEE105 Spring 2008 Lecture 23, Slide 1Prof. Wu, UC Berkeley• Reading: Chapter 10.4‐10.6.1Cascode Differential PairHalf circuit for ac analysis()313313313313||||||)]||(1[ππππrrrrrgRrrrrrgROOOmoutOOOmout+≅++=EE105 Spring 2008 Lecture 23, Slide 2Prof. Wu, UC Berkeley()[]31331311||||ππrrrrrggRgAOOOmmoutmv+−≅−=Telescopic Cascode Differential PairHalf circuit for ac analysisEE105 Spring 2008 Lecture 23, Slide 3Prof. Wu, UC Berkeley()[][ ])||(||||575531331ππrrrgrrrggAOOmOOmmv−≈Example[]()opOOmmvOOOmopRrrrggARrrrRrrgR||)||(2||||2||||13133115751575πππ−=+⎥⎦⎤⎢⎣⎡⎟⎠⎞⎜⎝⎛+=Half circuit for ac analysisEE105 Spring 2008 Lecture 23, Slide 4Prof. Wu, UC Berkeley4/29/2008EE105 Fall 2007 2Effect of Finite Tail Impedance• If the tail current source is not ideal, then when an input common‐mode voltage is applied, the currents in Q1 and Q2 and hence the output common‐mode voltage will change.EE105 Spring 2008 Lecture 23, Slide 5Prof. Wu, UC Berkeley()EEmCEEmCCMinCMoutRgRRgRVV21212/,,+−=+−=ΔΔCommon-mode gain should be smallEffect of Input CM Noise Ideal Tail Current• There is no effect of the input CM noise at the output.EE105 Spring 2008 Lecture 23, Slide 6Prof. Wu, UC BerkeleyEffect of Input CM NoiseNon‐Ideal Tail Current • The single‐ended outputs are corrupted by the input CM noise.2TAILIPTAIL EEEEVIIR=+EE105 Spring 2008 Lecture 23, Slide 7Prof. Wu, UC Berkeley• Tail current, ITAIL, now changes with VP, and VPis affected by VCMTAILIComparison • The differential output voltage signal is the same for both casesIdeal Tail Current Non-Ideal Tail CurrentEE105 Spring 2008 Lecture 23, Slide 8Prof. Wu, UC Berkeleyfor both cases.Æ For small input CM noise, the differential pair is not affected.4/29/2008EE105 Fall 2007 3CM to DM Conversion; gain ACM‐DM• If finite tail impedance and asymmetry (e.g. in load resistance) are both present, then the differential output signal willcontain a portion of the input common‐mode signal.CMCEECmCEECBECMRVIRIgIRIVV2122+Δ=Δ⇒Δ+Δ=Δ+Δ=ΔEE105 Spring 2008 Lecture 23, Slide 9Prof. Wu, UC Berkeley()EEmCCMoutRgRVV2/1 +Δ=ΔΔEEmRg2+() 2121CCoutoutoutCCCoutCCoutRIVVVRRIVRIVΔΔ−=Δ−Δ=ΔΔ+Δ−=ΔΔ−=ΔCIΔCIΔExampleEE105 Spring 2008 Lecture 23, Slide 10 Prof. Wu, UC Berkeley{}31 3 3 1 3112 [1 ( || )] ||CCM DMmOmRAgRr r Rrgππ−Δ=++ +• CMRR is the ratio of the wanted amplified differential input signal to the unwanted converted input common‐mode noise that appears at the output.Common‐Mode Rejection Ratio DMCMDMAACMRR−≡EE105 Spring 2008 Lecture 23, Slide 11 Prof. Wu, UC BerkeleyDifferential to Single‐Ended Conversion• Many circuits require a differential to single‐ended conversion.EE105 Spring 2008 Lecture 23, Slide 12 Prof. Wu, UC Berkeley• This topology is not very good; its most critical drawback is supply noise corruption, since no common‐mode cancellation mechanism exists. Also, we lose half of the voltage signal.4/29/2008EE105 Fall 2007 4… A Better Alternative• This circuit topology performs differential to single‐ended conversion with no loss of gain.(),,12outmoNPNoPNPin invgr rvv=−EE105 Spring 2008 Lecture 23, Slide 13 Prof. Wu, UC BerkeleyActive Load• With a current mirror as the load, the signal current produced by Q1 can be replicated onto Q4.• This type of load is different from the conventional “static load” and is called an “active load.”EE105 Spring 2008 Lecture 23, Slide 14 Prof. Wu, UC BerkeleyDifferential Pair with Active Load• The input differential pair decreases the current drawn from RL by ΔI, and the active load pushes an extra ΔI into RL by current mirror action; these eff ects enhance each other.EE105 Spring 2008 Lecture 23, Slide 15 Prof. Wu, UC BerkeleyActive Load vs. Static Load• The load in the circuit on the left responds to the input signal and enhances the single‐ended output, whereas the load in the circuit on the right does not.EE105 Spring 2008 Lecture 23, Slide 16 Prof. Wu, UC
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