1 of 5Experiment 9Multistage AmplifiersW.T. Yeung, J.C. Rudell, and R.T. HoweUC Berkeley EE 105Spring 20051.0 ObjectiveIn Exps. 7 and 8, you found the small signal properties of single stage amplifiers (e.g.,Common Emitter, Common Collector, Common Drain, etc.) Now you will see howthese single stage amplifiers perform together. By cascading the single stage devices,new amplifiers with enhanced performance can be realized. You will also study theeffects of loading between stages.To show your understanding of the lab, your write-up should contain:• A discussion on how single stages interact together• A discussion on interstage loading based on 2-port models2.0 Prelab• H & S: Chapter 9• For the Cascode Circuit in Fig. 1, hand-calculate the gain, input resistance and out-put resistance for a supply current of ISUP = 1 mA.(Use npn: βn = 80, VAn = 50 V, - pnp: βp = 30, VAp =15 V.)Given: the current-source supply in figure 1 has a small-signal resistance roc = βprop.Procedure2 of 5 Experiment 9 Multistage AmplifiersFIGURE 1. Cascode Amplifier with Current Source Supply3.0 Procedure3.1 The CascodeThe Cascode circuit is nothing more than a Common Emitter - Common Base (or Com-mon Source - Common Gate) cascade. Figure 1 above shows a simplified cascode witha current source load.The 2 port model for the cascode is shown belowFIGURE 2. 2-Port Representation of CascodeQ1M3501Q2M3501VBIASVCCvINvOUT250kΩ10µF1 MΩISUPRinGmRoutRin-iin2RoutCommon Emitter StageCommon Base StageRLProcedureExperiment 9 Multistage Amplifiers 3 of 5In your lab, the cascode circuit will include extra biasing circuits as shown in Fig. 3. These circuits make use of DC feedback (coupled through the external low-pass filter), in order to stabilize this high-gain circuit. After simplification, Fig. 3 reduces to the basic cascode amplifier in Fig. 1 for the frequencies we will be concerned with.1. Set up the circuit from Lab Chip 4 as shown in Fig. 3. Let RBias be 10 kΩ.and Cin be 10 µF. Let VCC be set at 3.5 V. Note: The user just needs to furnish the external ele-ments in the box. (the elements in the dashed “boxes” in Fig. 3).2. Determine the bias current and DC voltage at VOUT. Using Fig. 3, what are the maxi-mum and minimum DC voltages that VOUT can swing to while keeping all the devices in the forward active region. Compare with measurements of output clipping levels. 3. Using the oscilloscope, find the gain vout/vin. Use a 5 kHz sine wave with an ampli-tude of 65 mV. If the signal at the output is clipped, decrease the input amplitude until no clipping occurs. 4. Calculate the input resistance and output resistance for the cascode. Using the calcu-lated value of the input resistance, you can calculate how much of the input voltage is attenuated. Determine the gain of the cascode vout/vin. How does the cascode com-pare to the Common Emitter in terms of input resistance, output resistance and volt-age gain? Optional: measure the input and the output resistances. FIGURE 3. Bipolar Cascode with DC Feedback Biasing (Lab Chip 4)Q6Q1Q5Q7Q2R290kΩ=IBIASR63.75kΩ=Rlp5MegΩ=RBiasR190kΩ=Clp10u=M3501M3501M3501M3511M3511VCC = 3.5 VPIN 17GNDPIN 15PIN 28PIN 18PIN 14PIN 19Q3Q4M3501M3511R3R4R5250Ω250Ω250ΩPIN 16M9CinvinRS = 1 MΩOff-chip components: input signal, setting DCoperating point of cascode vINvOUTM2Procedure4 of 5 Experiment 9 Multistage AmplifiersFind the DC voltage at vOUT (PIN 17) and make sure that Q3 and Q4 are not saturated. If they are, get a new chip.The circuit takes about 10 - 20 seconds to stabilize. Be patient.5. Perform a SPICE analysis on the Cascode in Fig. 1 (the circuit in Fig. 3 is extra credit) and compare your results with simulation.3.2 Cascading Stages1. While leaving the Cascode intact, build the common emitter as shown in Fig. 4; do not include the coupling capacitor yet. Set RBIAS (CEBIASP) to be a potentiometer and adjust it until the output is at 2.5V. (This is merely the same procedure as the common emitter circuit in Exp. 7.) Find the bias current through RBIAS. Does the DC voltage at VOUT confirm the fact that IC = IBIAS? Find the gain of the Common Emit-ter.2. Now cascade the two stages together with the use of the 10 µF coupling capacitor. What is its function? (Hint: look at the DC voltage at both sides of the capacitor) What would happen if the capacitor were not present? Change the amplitude of the sinusoid to 50 mV.3. Find the gain for the cascade. Measure the gain vout1 / vin. Why is it reduced?FIGURE 4. Cascode - Common Emitter CascadeLab TipQ1M3501Q2M3501VBIASVCC = 3.5 VPIN 19PIN 17VCC5V=RC10kΩ=vbGround = PIN 1410 µFISUPIC is controlled byRBIAS between CE_BIAS(PIN 27) and VCC. Lab Chip 4Lab Chip 3PIN 26vOUT2PIN 25vOUT1vINPIN 28PIN 28+_vinOptional ExperimentsExperiment 9 Multistage Amplifiers 5 of 54. Draw the 2 port models for the cascaded amplifier in Fig. 4. Comment on the overall gain and the loading between stages.4.0 Optional Experiments4.1 Common Collector as a Buffering Stage1. Leaving the cascode and common emitter circuit intact, we now insert a Common Collector as an intermediate stage between the Cascode and Common Emitter. Find the gain of this new circuit. For the Common Collector, set RBIAS = 100 kΩ. For mea-suring input attenuation, the source resistance may have to be increased over the value in Fig. 3. Lower the amplitude of the input sinusoid and reduce the source resistance as necessary to avoid clipping at the output.2. Draw the 2-port models for this Cascode-CC-CE configuration. Comment on the gain and the interstage loading.FIGURE 5. Common Collector (Emitter Follower) Voltage Buffer (Lab Chip 4)10 µFVCC5V=vbIBIASIBIAS is controlled by RBIASbetween EF_BIAS (PIN 25)RC10kΩ=vin3vOUTGround = PIN 14PIN 25 (chip 3)PIN 23PIN 24and VCC (PIN 28) on Lab Chip 4PIN 26 (chip
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