Experiment 9 Multistage Amplifiers W T Yeung J C Rudell and R T Howe UC Berkeley EE 105 Spring 2005 1 0 Objective In Exps 7 and 8 you found the small signal properties of single stage amplifiers e g Common Emitter Common Collector Common Drain etc Now you will see how these single stage amplifiers perform together By cascading the single stage devices new amplifiers with enhanced performance can be realized You will also study the effects of loading between stages To show your understanding of the lab your write up should contain A discussion on how single stages interact together A discussion on interstage loading based on 2 port models 2 0 Prelab H S Chapter 9 For the Cascode Circuit in Fig 1 hand calculate the gain input resistance and output resistance for a supply current of ISUP 1 mA Use npn n 80 VAn 50 V pnp p 30 VAp 15 V Given the current source supply in figure 1 has a small signal resistance roc prop 1 of 5 Procedure FIGURE 1 Cascode Amplifier with Current Source Supply VCC ISUP vOUT 10 F 250k M3501 Q2 V BIAS 1 M vIN Q1 M3501 3 0 Procedure 3 1 The Cascode The Cascode circuit is nothing more than a Common Emitter Common Base or Common Source Common Gate cascade Figure 1 above shows a simplified cascode with a current source load The 2 port model for the cascode is shown below FIGURE 2 2 Port Representation of Cascode Rin Gm Rout Common Emitter Stage 2 of 5 Experiment 9 Multistage Amplifiers Rin iin2 Common Base Stage Rout RL Procedure In your lab the cascode circuit will include extra biasing circuits as shown in Fig 3 These circuits make use of DC feedback coupled through the external low pass filter in order to stabilize this high gain circuit After simplification Fig 3 reduces to the basic cascode amplifier in Fig 1 for the frequencies we will be concerned with 1 Set up the circuit from Lab Chip 4 as shown in Fig 3 Let RBias be 10 k and Cin be 10 F Let VCC be set at 3 5 V Note The user just needs to furnish the external elements in the box the elements in the dashed boxes in Fig 3 2 Determine the bias current and DC voltage at VOUT Using Fig 3 what are the maxi mum and minimum DC voltages that VOUT can swing to while keeping all the devices in the forward active region Compare with measurements of output clipping levels 3 Using the oscilloscope find the gain vout vin Use a 5 kHz sine wave with an ampli tude of 65 mV If the signal at the output is clipped decrease the input amplitude until no clipping occurs 4 Calculate the input resistance and output resistance for the cascode Using the calcu lated value of the input resistance you can calculate how much of the input voltage is attenuated Determine the gain of the cascode vout vin How does the cascode compare to the Common Emitter in terms of input resistance output resistance and voltage gain Optional measure the input and the output resistances FIGURE 3 Bipolar Cascode with DC Feedback Biasing Lab Chip 4 Off chip components input signal setting DC operating point of cascode VCC 3 5 V PIN 28 Q5 M3511 I BIAS Q6 R Bias M3511 Q4 PIN 17 vOUT vin PIN 16 R1 90k R2 M3501 Q3 90k Q7 R4 250 vIN PIN 19 Q2 M3501 Cin RS 1 M M3511 R5 250 M3501 M9 R lp R3 250 Q1 M3501 Experiment 9 Multistage Amplifiers PIN 18 R6 5Meg PIN 15 C lp M2 10u 3 75k GND PIN 14 3 of 5 Procedure Lab Tip Find the DC voltage at vOUT PIN 17 and make sure that Q3 and Q4 are not saturated If they are get a new chip The circuit takes about 10 20 seconds to stabilize Be patient 5 Perform a SPICE analysis on the Cascode in Fig 1 the circuit in Fig 3 is extra credit and compare your results with simulation 3 2 Cascading Stages 1 While leaving the Cascode intact build the common emitter as shown in Fig 4 do not include the coupling capacitor yet Set RBIAS CEBIASP to be a potentiometer and adjust it until the output is at 2 5V This is merely the same procedure as the common emitter circuit in Exp 7 Find the bias current through RBIAS Does the DC voltage at VOUT confirm the fact that IC IBIAS Find the gain of the Common Emitter 2 Now cascade the two stages together with the use of the 10 F coupling capacitor What is its function Hint look at the DC voltage at both sides of the capacitor What would happen if the capacitor were not present Change the amplitude of the sinusoid to 50 mV 3 Find the gain for the cascade Measure the gain vout1 vin Why is it reduced FIGURE 4 Cascode Common Emitter Cascade Lab Chip 4 PIN 28 PIN 28 V CC 5V VCC 3 5 V R C 10k ISUP vOUT1 PIN 17 M3501 Q2 V BIAS PIN 19 PIN 26 10 F 4 of 5 vIN PIN 27 and VCC PIN 25 vb Ground PIN 14 Q1 vin vOUT2 IC is controlled by RBIAS between CE BIAS M3501 Experiment 9 Multistage Amplifiers Lab Chip 3 Optional Experiments 4 Draw the 2 port models for the cascaded amplifier in Fig 4 Comment on the overall gain and the loading between stages 4 0 Optional Experiments 4 1 Common Collector as a Buffering Stage 1 Leaving the cascode and common emitter circuit intact we now insert a Common Collector as an intermediate stage between the Cascode and Common Emitter Find the gain of this new circuit For the Common Collector set RBIAS 100 k For measuring input attenuation the source resistance may have to be increased over the value in Fig 3 Lower the amplitude of the input sinusoid and reduce the source resistance as necessary to avoid clipping at the output 2 Draw the 2 port models for this Cascode CC CE configuration Comment on the gain and the interstage loading FIGURE 5 Common Collector Emitter Follower Voltage Buffer Lab Chip 4 V CC 5V IBIAS is controlled by RBIAS between EF BIAS PIN 25 and VCC PIN 28 on Lab Chip 4 R C 10k PIN 23 vb IBIAS PIN 24 PIN 26 chip 3 10 F v OUT PIN 25 chip 3 v in3 Ground PIN 14 Experiment 9 Multistage Amplifiers 5 of 5
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