EE105 Fall 2006 Microelectronic Devices and Circuits Prof Jan M Rabaey jan eecs Lecture 26 Bipolar Junction Transistor Amplifiers Frequency Response Lecture Material Last lecture BJT amplifiers This lecture Emitter degenerated CE Amplifier Frequency response of BJT Amplifiers Designing complex amplifiers 2 1 Administrativia Lab 8 this week Lab 9 next week no written report just oral at end of lab session Last homework will be posted this week No lecture on Tu Dec 5 Make up lecture scheduled tentatively for December 11 at 2pm 203 McLaughlin Final We December 13 12 30 3 30pm 105 North Gate 3 Schedule for the rest of the semester Tu 11 27 BJT Amplifiers continued Complex amplifiers start Th 11 29 Complex amplifiers Advanced topics start Th Dec 7 Advanced topics cntd Mo Dec 11 Semester overview and review session 4 2 One Last Exercise Common Collector Voltage Gain KCL at the output node note v vt vout 5 Summary of Two Port Parameters for CE CS CB CG CC CD 6 3 Frequency Response of Common Emitter 7 Frequency Response of Common Emitter 8 4 Assuming Rsig to be small 9 BJT Biasing Discrete 10 5 BJT Biasing 2 11 Common Emitter with Emitter Degeneration 1 What is it 2 DC Bias 3 Small signal 2 port model 4 Output swing 12 6 DC Bias for CEdeg 13 CE degen Biasing 14 7 Two Port Model for CEdeg Input looks like CC Rin Output looks like CB see p 504 for details Rout Transconductance Gm 15 Two Port Model for CEdeg cont Find Gm Voltage Gain Is it a good voltage amplifier vs CE 16 8 Temperature Dependence Gm of Bipolar strong function of temperature 17 Analyzing Complex Amplifiers Example Discrete VHF Amplifier 18 9 Multi Stage Voltage Amplifier 19 Cutting Through the Complexity Two Approaches 1 Eliminate background transistors to reduce clutter 2 Identify the signal path between the input and output 20 10 First Approach Find I V Sources 21 What s Left Voltage at base of Q2 is set by totem pole 22 11 Second Approach Find Signal Path 23 Identifying the Stages First stage or two stages CS CB cascode Second stage or two stages CD CC voltage buffer Why does this make sense for a voltage amplifier 24 12 Find Key Two Port Parameters Output resistance of cascode Rout CS CB roc ro 2 1 g m 2 r 2 RS 2 roc Rup ro 6 1 g m 6RS 6 25 Two Port Parameters Cont 26 13 Output Resistance and Voltage Gain Source resistance of the CC stage is the output resistance of the CD stage small Rout Rout CC R 1 1 1 S CC gm4 o g m 4 g m 3 o g m 4 1 Open circuit voltage gain Av last two stages have nearly unity gain Av g m1 o ro 2 ro 6 1 g m 6ro 7 27 Output Swing VOUT MIN Minimum output voltage M10 M3 and Q2 are suspects M10 goes into triode when VOUT 0 5 V M3 goes into triode when VSD3 0 5 V VOUT 0 5 V 0 7 V 0 2 V Q2 goes into saturation when VCE2 0 1 V or VBC2 0 6 V VOUT VB2 VBC2 VSG3 VBE4 2 V 0 6 V 1 5 V 0 7 V VOUT 2 2 V 28 14 Output Swing VOUT MAX Maximum output voltage Q4 M5 and M6 are suspects Q4 goes into saturation when VCE4 0 1 V VOUT 4 9 V M5 goes triode when VSD5 0 5 V VOUT 3 8 V M6 goes triode when VSD6 0 5 V VOUT VS6 0 5 V VSG3 VBE4 3 5 0 5 1 5 0 7 V 3 8 V 29 Insight into the Frequency Response 30 15 Qualitative Insight Could always do brute force open circuit time constants CS CB is a wideband stage so is the CD CC buffer Look for large RTxCx products high impedance nodes are likely candidates 31 Node X High impedance node is node X look at RTxCx Capacitance Cx Cgd6 C 2 Cgd3 CM3 Miller for CD stage M3 32 16 Finding the Miller Capacitance CM3 Cgs3 X CD RL3 R L3 Gain across Cgs3 AvC gs 3 1 g m 3 R L 3 RL3 Rin4 33 Dominant Pole of Voltage Amplifier Th venin resistance for CX RTx Rout 2 R in 3 Rout CB R in CD RTx roc ro 2 1 g m 2 r 2 RS 2 ro 6 1 g m 6ro 7 ro 2 o Dominant pole 1 1 RTx C x 34 17
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