1EE105 - Fall 2006Microelectronic Devices and CircuitsProf. Jan M. Rabaey (jan@eecs)Lecture 26: Bipolar Junction TransistorAmplifiers – Frequency Response2Lecture Material Last lecture– BJT amplifiers This lecture– Emitter-degenerated CE Amplifier– Frequency response of BJT Amplifiers– Designing complex amplifiers23Administrativia Lab 8 this week Lab 9 next week (no written report – just oral at end of lab session) Last homework will be posted this week No lecture on Tu Dec 5 – Make-up lecture scheduled tentatively for December 11 at 2pm (203 McLaughlin) Final: We December 13, 12:30-3:30pm, 105 North Gate4Schedule for the rest of the semester Tu 11/27: BJT Amplifiers (continued) – Complex amplifiers (start) Th 11/29: Complex amplifiers; Advanced topics (start) Th Dec 7: Advanced topics (cntd) Mo Dec 11: Semester overview and review session35One Last Exercise: Common-Collector Voltage GainKCL at the output node: note vπ= vt- vout6Summary of Two-Port Parameters for CE/CS, CB/CG, CC/CD47Frequency Response of Common-Emitter8Frequency Response of Common-Emitter59Assuming Rsig to be small 10BJT Biasing (Discrete)611BJT Biasing (2)12Common-Emitter with Emitter Degeneration1. What is it?2. DC Bias3. Small-signal 2-portmodel4. Output swing713DC Bias for CEdeg14CE(degen) Biasing815Two-Port Model for CEdeg Input looks like CC Æ Rin= Output looks like CB (see p. 504 for details) Æ Rout= Transconductance: Gm= 16Two-Port Model for CEdeg(cont.) Find Gm Voltage Gain: Is it a good voltage amplifier (vs. CE)?917Temperature Dependence Gm of Bipolar strong function of temperature18Analyzing Complex AmplifiersExample: Discrete VHF Amplifier1019Multi-Stage Voltage Amplifier20Cutting Through the ComplexityTwo Approaches:1. Eliminate “background” transistors to reduceclutter2. Identify the “signal path” between the inputand output1121First Approach: Find I & V Sources22What’s Left? Voltage at base ofQ2is set by totempole1223Second Approach: Find Signal Path24Identifying the StagesFirst stage (or two stages): CS/CB cascodeSecond stage (or two stages): CD/CC voltage bufferWhy does this make sense for a voltage amplifier?1325Find Key Two-Port ParametersOutput resistance of cascode:(){}2222/,||1(||SmoocCBCSoutRrgrrRπ+=()6661SmoupocRgrRr +==26Two-Port Parameters (Cont.)1427Output Resistance and Voltage GainSource resistance of the CC stage is the output resistanceof the CD stage (small)434,4,1111mommoCCSmCCoutoutgggRgRR ≈β+=β+==Open-circuit voltage gain Av(last two stages have nearly unity gain): ()()766211||omooomvrgrrgA +β−=28Output Swing: VOUT,MINMinimum output voltage: M10, M3, and Q2are “suspects”M10goes into triode when VOUT= 0.5 VM3goes into triode when VSD3= 0.5 V ÆVOUT= 0.5 V – 0.7 V = -0.2 VQ2goes into saturation when VCE2= 0.1 Vor VBC2= 0.6 VVOUT= VB2– VBC2+ VSG3– VBE4= 2 V – 0.6 V + 1.5 V – 0.7 VVOUT= 2.2 V1529Output Swing: VOUT,MAXMaximum output voltage: Q4, M5, and M6are “suspects”Q4 goes into saturation when VCE4= 0.1 V Æ VOUT= 4. 9 VM5goes triode when VSD5= 0.5 V Æ VOUT= 3.8 VM6goes triode when VSD6= 0.5 V ÆVOUT= VS6– 0.5 V + VSG3– VBE4= 3.5 – 0.5 + 1.5 – 0.7 V = 3.8 V30Insight into the Frequency Response1631Qualitative InsightCould always do “brute force” open-circuit time constantsCS*-CB is a wideband stage … so is the CD-CC bufferLook for large RTxCxproducts: high-impedance nodesare likely candidates32Node X“High impedance node” is node X … look at RTxCxCapacitance:Cx= Cgd6+ Cμ2+ Cgd3+ CM3Miller for CDstage (M3)1733Finding the Miller Capacitance CM3Gain across Cgs3: 3333/1LmLgsvCRgRA+= CD X Cgs3 RL3 RL3= Rin4 = 34Dominant Pole of Voltage AmplifierCDinCBoutinoutTxRRRRR,,32|||| ==ooomoSmoocTxrrgrRrgrrR β+≅+=π 27662222||)1())||(1(||Thévenin resistance for CX:Dominant
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