1EE105 - Fall 2005Microelectronic Devices and CircuitsLecture 8MOS TransistorMOS Sample and Hold2AnnouncementsHomework 4 due next weekLab 2 this weekReading: Chapter 4Check out the IC seminar series, Monday 4-5pm in the Hogan Rm (531 Cory)9/26 – Rick Livengood, Intel on cool methods in chip testing and repair23Lecture MaterialLast lectureMOS TransistorThis lectureMOS I-V relationshipSample and hold18Sample & Hold FunctionGoal: charge up load capacitor to input voltage rapidly when control voltage is switched on; hold voltage on capacitor when control is switched offApplications: analog-to-digital converters + - vs(t) vGB(t) + - vl(t) CL319Linear Model: vssmallInitial condition: vl= 0 VGate voltage steps from 0 V to VDD= 2.5 VDSDSTnGSoxnDvvVvLWCi ))(/(−−=µGate-source voltage: vGS= VDD– vlÆDrain-source voltage: vDS= vs- vl))]()(/([lsTnDDoxnDvvVVLWCi−−≈µ20Equivalent Circuit+ - vs(t) vl(t) CL RDS ){}1)(/(−−=TnDDoxnDSVVLWCRµ421ExampleµnCox= 50 µA/V2, VGS= VDD= 2.5 V, VTn= 0.5 V,L = 0.6 µm If we want RDS= 100 Ω, then the MOSFET width must be:()[][]mVVCRLWTnDDoxnDSµµ60)2(10501006.06=⋅=−=−For an efficient layout, this transistor with W/L = 100 shouldbe folded … see example in Chapter 4.22Example Waveformtvl(t)50 mV)1()(/LDSCRtslevtv−−=50 mVτ= RDSCL0.63(50) =31.5 mV523Sampling ErrorAbsolute error = e = vl- vsRelative error = ε = e / vs()sCRtssvevvLDSs/1−−−=ε, where tsis the sampling time(time interval where VGS= VDD)LDSsCRte/−=εExample case: RDS= 100 Ω, CL= 500 fF Æ τ = 50 psFor 16 bit precision, we need the relative error ε < 2-16= 1.5 x 10-5= 15 ppm (parts per million) Æ()psts554)1.11(ln==−=τετ24Sampling Large VoltagesIf the source (a.k.a. input) voltage is not small Æ need to use the full model for the MOSFET()( )22)/(2LTnDDTnGSoxnDvVVKVvLWCi −−=−=µdtdvCtiLLD=)(vDS= VDD – vL> VDD– vL– VTn= vGSÆ saturated, as long as vGS> VTn()dtdvCvVVKLLLTnDD=−−2()∫∫′−−′=′lvoLTnDDLLtvVVKvdCtd20625Solve for Load Voltage()()()TnDDLLTnDDLvoLTnDDLLtVVKCvVVKCvVVKvdCttdl−−−−−−=′−−′==′∫∫20()( )()( )()( )LTnDDTnDDLLLTnDDTnDDLTnDDLTnDDLvVVVVKvCvVVVVKvVVCVVCt−−−=−−−−−−−=()()[]LLLTnDDTnDDvCvVVKVVKt =−−−2()[]()2TnDDLTnDDLVVtKCVVKtv −−=−−−()()[]()⎟⎟⎠⎞⎜⎜⎝⎛⎭⎬⎫⎩⎨⎧−=+⋅==+−−=tVVtiCCttiCtVVKtVVKtvTnDDDLLDLTnDDTnDDL)0(/11)0()(226Sampled Voltage WaveformtvL(t)1.5 VvLapproaches VDD– VTn= 1.5 V (for vS= VDD)µnCox= 50 µA/V2, (W/L) = 100 Æ iD(t = 0) = 5.6 mASlope = iD(t = 0)/CLvGS= VDD– vL– VTnÆiD(t)VTnt = 0Less thanVDD727Improved Sample and Hold NMOS and PMOS transistors in parallel Æ sampled voltage canbe pulled up to the supply voltage and pulled down to ground.+ - vs(t) φ vl(t)
View Full Document
Unlocking...