EE105 Fall 2005 Microelectronic Devices and Circuits Lecture 8 MOS Transistor MOS Sample and Hold Announcements Homework 4 due next week Lab 2 this week Reading Chapter 4 Check out the IC seminar series Monday 4 5pm in the Hogan Rm 531 Cory 9 26 Rick Livengood Intel on cool methods in chip testing and repair 2 1 Lecture Material Last lecture MOS Transistor This lecture MOS I V relationship Sample and hold 3 Sample Hold Function Goal charge up load capacitor to input voltage rapidly when control voltage is switched on hold voltage on capacitor when control is switched off Applications analog to digital converters vGB t vs t CL vl t 18 2 Linear Model vs small Initial condition vl 0 V Gate voltage steps from 0 V to VDD 2 5 V iD nCox W L vGS VTn vDS vDS Gate source voltage vGS VDD vl Drain source voltage vDS vs vl iD nCox W L VDD VTn vs vl 19 Equivalent Circuit RDS vs t CL vl t RDS nCox W L VDD VTn 1 20 3 Example nCox 50 A V2 VGS VDD 2 5 V VTn 0 5 V L 0 6 m If we want RDS 100 then the MOSFET width must be L 0 6 60 m RDS nCox VDD VTn 100 50 10 6 2 W For an efficient layout this transistor with W L 100 should be folded see example in Chapter 4 21 Example Waveform vl t 50 mV 0 63 50 31 5 mV RDSCL vl t vs 1 e t RDS C L 50 mV t 22 4 Sampling Error Absolute error e vl vs Relative error e vs vs vs 1 e t s RDS CL vs e t s where ts is the sampling time time interval where VGS VDD RDS C L Example case RDS 100 CL 500 fF 50 ps For 16 bit precision we need the relative error 2 16 1 5 x 10 5 15 ppm parts per million t s ln 11 1 554 ps 23 Sampling Large Voltages If the source a k a input voltage is not small need to use the full model for the MOSFET vDS VDD vL VDD vL VTn vGS saturated as long as vGS VTn iD nCox 2 iD t C L W L vGS VTn K VDD VTn vL 2 2 dvL dt K VDD VTn vL C L 2 dvL dt t 0 dt vl o C L dv L 2 K VDD VTn v L 24 5 Solve for Load Voltage t 0 dt t t vl o CL CL C L dv L 2 K VDD VTn vL K VDD VTn K VDD VTn v L C L VDD VTn C L VDD VTn vL C L vL K VDD VTn VDD VTn vL K VDD VTn VDD VTn vL t K VDD VTn K VDD VTn vL C L vL 2 vL Kt VDD VTn C L tK VDD VTn 2 K VDD VTn t vL t K VDD VTn t C L 2 iD t 0 t 1 C L iD t 0 1 t CL VDD VTn 25 Sampled Voltage Waveform t 0 iD t vL t 1 5 V VTn vGS VDD vL VTn Less than VDD Slope iD t 0 CL vL approaches VDD VTn 1 5 V for vS VDD t nCox 50 A V2 W L 100 iD t 0 5 6 mA 26 6 Improved Sample and Hold NMOS and PMOS transistors in parallel sampled voltage can be pulled up to the supply voltage and pulled down to ground vs t CL vl t 27 7
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