EE105 - Fall 2006Microelectronic Devices and CircuitsProf. Jan M. Rabaey (jan@eecs)Lecture 7: MOS Transistor2Some Administrative Issues Lab 2 this week Hw 2 due on We – Hw 3 will be posted same day MIDTERM 1 next week Th – will cover everything up to and including MOSCAP Otherwise very normal week …3Overview Last lecture– MOS Capacitor This lecture– MOS Transistor4MOS-CAP : Fields and Charge at Equilibrium At equilibrium there is an electric field from the gate to the body. The charges on the gate are positive. The negative charges in the body come from a depletion regionBody (p-type substrate)++++++++++++++++++−−−−−−−−−−−−−−−−−−−−−−−−−−0dX+−oxV+−BVoxEBuilt-in Voltage: Approx 970 mV5Good Place to Sleep: Flat Band If we apply a bias, we can compensate for this built-in potential In this case the charge on the gate goes to zero and the depletion region disappears In solid-state physics lingo, the energy bands are “flat”under this condition()FBpnVφφ+=− −()0GGB FBQV V==Body (p-type substrate)+−0FBV <6Accumulation If we further decrease the potential beyond the “flat-band” condition, we essentially have a parallel plate capacitor Plenty of holes and electrons are available to charge up the plates Negative bias attracts holes under gate()Gox GB FBQCV V=−Body (p-type substrate)−+GBFBVV<++++++++++++++++++−−−−−−−−−−−−−−−−−−BGQQ=7Depletion Similar to equilibrium, the potential in the gate is higher than the body Body charge is made up of the depletion region ions Potential drop across the body and depletion regionBody (p-type substrate)+−GBFBVV>+ + + + + + + + + +()Bad GBQqNXV=−−−−−−−−−−−−−−−−−−()GGBBQVQ=−8Body (p-type substrate)+ + + + + + + + + +Inversion As we further increase the gate voltage, eventually the surface potential increases to a point where the electron density at thesurface equals the background ion density At this point, the depletion region stops growing and the extra charge is provided by the inversion charge at surface+−GBTVV=−−−−−−−−−−−−−−−−−sqkTsianne Nφ==spφφ=−sφ9Threshold Voltage The threshold voltage is defined as the gate-body voltage that causes the surface to change from p-type to n-type For this condition, the surface potential has to equal the negative of the p-type potential We’ll derive that this voltage is equal to:122(2)TnFB p sa poxVV qNCφεφ=−+ −10Q-V Curve for MOS Capacitor In accumulation, the charge is simply proportional to the applies gate-body bias In inversion, the same is true In depletion, the charge grows slower since the voltage is applied over a depletion regionGQ()GBVVTnVFBVinversionaccumulationdepletion,maxBQ−()NGBQV−11MOS CV Curve Small-signal capacitance is slope of Q-V curve Capacitance is linear in accumulation and inversion Capacitance in depletion region is smallest Capacitance is non-linear in depletionGQ()GBVVTnVFBV,maxBQ−()NGBQV−CGBVoxCoxCTnVFBV12C-V Curve Equivalent Circuits In accumulation mode the capacitance is just due to the voltage drop across tox In inversion the incremental charge comes from the inversion layer (depletion region stops growing). In depletion region, the voltage drop is across the oxide and the depletion regionoxCoxCoxCdepCsdepdepCxε=11dep oxox oxtotdep s oxdep oxoxdepoxCCCCCCtCCxCεε===+++13The MOSFET Transistor The symbols with the arrows are typically used in analog applications The body contact is often not shown The source/drain can switch depending on how the device is biased (the device has inherent symmetry)NMOS PMOS14Observed Behavior: ID-VGS Current zero for negative gate voltage Current in transistor is very low until the gate voltage crosses the threshold voltage of device (same threshold voltage as MOS capacitor) Current increases rapidly at first and then it finally reaches a point where it simply increases linearlyGSVDSITVGSVDSIDSV15Observed Behavior: ID-VDS For low values of drain voltage, the device is like a resistor As the voltage is increases, the resistance behaves non-linearly and the rate of increase of current slows Eventually the current stops growing and remains essentially constant (current source)DSV/DSIk“constant” currentresistor regionnon-linear resistor region2GSVV=3GSVV=4GSVV=GSVDSIDSV16MOSFET Cross Section Add two junctions around MOS capacitor The regions forms PN junctions with substrate MOSFET is a four terminal device The body is usually grounded (or at a DC potential) For ICs, the body contact is at surfacep-type substraten+n+source draindiffusion regionsgatebodyp+L17MOSFET Layout Planar process: complete structure can be specified by a 2D layout Design engineer can control the transistor width W andL Process engineer controls tox, Na, xj, etc.p-type substraten+n+SDGBp+BSDLLWcontactpoly gatejxG18PMOS & NMOS A MOSFET by any other name is still a MOSFET:– NMOS, PMOS, nMOS, pMOS– NFET, PFET– IGFET– Other flavors: JFET, MESFET CMOS technology: The ability to fabricated NMOS and PMOS devices simultaneouslyn-type substratep+p+SDBn+LjxPMOSGp-type substraten+n+SDGBp+Ljx19CMOS Complementary MOS: Both P and N type devices Create a n-type body in a p-type substrate through compensation. This new region is called a “well”. To isolate the PMOS from the NMOS, the well must be reverse biased (pn junction)p-type substratep-type substraten+n+SDGBp+Ljxn-type substratep+p+SDBn+LjxPMOSG20“Linear” Region Current If the gate is biased above threshold, the surface is inverted This inverted region forms a channel that connects the drain and gate If a drain voltage is applied positive, electrons will flow from source to drainp-typen+n+p+Inversion layer“channel”GSTnVV>100mVDSV ≈GDSNMOSxy21MOSFET “Linear” Region The current in this channel is given by The charge proportional to the voltage applied across the oxide over threshold If the channel is uniform density, only drift current flowsDSyNIWv Q=−()()NoxGSTnDSyoxGSTnQCVVIWv C V V=− −=−ynyvEμ=−DSyVEL=−GSTnVV>()DSnoxGSTnDSWICV VVLμ=−100mVDSV ≈22MOSFET: Variable Resistor Notice that in the linear region, the current is proportional to the voltage Can define a
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