EE105 Fall 2006 Microelectronic Devices and Circuits Prof Jan M Rabaey jan eecs Lecture 7 MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM 1 next week Th will cover everything up to and including MOSCAP Otherwise very normal week 2 Overview Last lecture MOS Capacitor This lecture MOS Transistor 3 MOS CAP Fields and Charge at Equilibrium Vox VB Body p type substrate Eox Xd0 At equilibrium there is an electric field from the gate to the body The charges on the gate are positive The negative charges in the body come from a depletion region Built in Voltage Approx 970 mV 4 Good Place to Sleep Flat Band QG VGB VFB 0 VFB 0 Body p type substrate If we apply a bias we can compensate for this built in potential VFB n p In this case the charge on the gate goes to zero and the depletion region disappears In solid state physics lingo the energy bands are flat under this condition 5 Accumulation QG Cox VGB VFB VGB VFB QB QG Body p type substrate If we further decrease the potential beyond the flatband condition we essentially have a parallel plate capacitor Plenty of holes and electrons are available to charge up the plates Negative bias attracts holes under gate 6 Depletion VGB VFB Body p type substrate QG VGB QB QB qN a X d VGB Similar to equilibrium the potential in the gate is higher than the body Body charge is made up of the depletion region ions Potential drop across the body and depletion region 7 Inversion s VGB VT Body p type substrate As we further increase the gate voltage eventually the surface potential increases to a point where the electron density at the surface equals the background ion density ns ni e q s kT Na s p At this point the depletion region stops growing and the extra charge is provided by the inversion charge at surface 8 Threshold Voltage The threshold voltage is defined as the gate body voltage that causes the surface to change from p type to n type For this condition the surface potential has to equal the negative of the p type potential We ll derive that this voltage is equal to 1 VTn VFB 2 p Cox 2q s N a 2 p 9 Q V Curve for MOS Capacitor QG n io s er v in tion e l p de c ac n io t a ul V um FB QN VGB QB max VTn VGB V In accumulation the charge is simply proportional to the applies gate body bias In inversion the same is true In depletion the charge grows slower since the voltage is applied over a depletion region 10 MOS CV Curve C QG Cox Cox QN VGB QB max VFB VTn VGB V VFB VTn VGB Small signal capacitance is slope of Q V curve Capacitance is linear in accumulation and inversion Capacitance in depletion region is smallest Capacitance is non linear in depletion 11 C V Curve Equivalent Circuits Cox Cox Cox Cdep s Cdep Cox Cox Cox Ctot xdep Cdep s tox Cdep Cox 1 1 ox xdep Cox In accumulation mode the capacitance is just due to the voltage drop across tox Cdep In inversion the incremental charge comes from the inversion layer depletion region stops growing In depletion region the voltage drop is across the oxide and 12 the depletion region The MOSFET Transistor NMOS PMOS The symbols with the arrows are typically used in analog applications The body contact is often not shown The source drain can switch depending on how the device is biased the device has inherent symmetry 13 Observed Behavior ID VGS I DS I DS VDS VGS VT VGS Current zero for negative gate voltage Current in transistor is very low until the gate voltage crosses the threshold voltage of device same threshold voltage as MOS capacitor Current increases rapidly at first and then it finally reaches a point where it simply increases linearly 14 Observed Behavior ID VDS I DS k non linear resistor region resistor region VGS 4V I DS constant current VDS VGS 3V VGS VGS 2V VDS For low values of drain voltage the device is like a resistor As the voltage is increases the resistance behaves non linearly and the rate of increase of current slows Eventually the current stops growing and remains essentially constant current source 15 MOSFET Cross Section gate body source drain diffusion regions p n L n p type substrate Add two junctions around MOS capacitor The regions forms PN junctions with substrate MOSFET is a four terminal device The body is usually grounded or at a DC potential For ICs the body contact is at surface 16 MOSFET Layout poly gate contact G B S p n B S G D D L n xj W p type substrate L Planar process complete structure can be specified by a 2D layout Design engineer can control the transistor width W and L Process engineer controls tox Na xj etc 17 PMOS NMOS G G B S p n D L n xj p type substrate B S n p D L p xj n type substrate PMOS A MOSFET by any other name is still a MOSFET NMOS PMOS nMOS pMOS NFET PFET IGFET Other flavors JFET MESFET CMOS technology The ability to fabricated NMOS and PMOS devices simultaneously 18 CMOS G G B S p n D L n xj p type substrate B S n p D L p xj n type substrate PMOS p type substrate Complementary MOS Both P and N type devices Create a n type body in a p type substrate through compensation This new region is called a well To isolate the PMOS from the NMOS the well must be reverse biased pn junction 19 Linear Region Current VGS VTn S p G D n y n p type NMOS VDS 100mV x Inversion layer channel If the gate is biased above threshold the surface is inverted This inverted region forms a channel that connects the drain and gate If a drain voltage is applied positive electrons will flow from source to drain 20 MOSFET Linear Region The current in this channel is given by I DS Wv y QN The charge proportional to the voltage applied across the oxide over threshold QN Cox VGS VTn I DS Wv y Cox VGS VTn If the channel is uniform density only drift current flows v y n E y I DS W nCox VGS VTn VDS L VDS Ey L VGS VTn VDS 100mV 21 MOSFET Variable Resistor Notice that in the linear region the current is proportional to the voltage I DS W nCox VGS VTn VDS L Can define a voltage dependent resistor VDS 1 L Req I DS nCox VGS VTn W L R VGS W This is a nice variable resistor electronically tunable 22 Finding ID f VGS VDS Approximate inversion charge QN y drain is higher than the source less charge at drain end of channel …
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