EECS 105 Fall1998Lecture 15Improved Inverter: Current-Source “Pull-Up”■ What else could be connected between the drain and VDD? Samll-signal (incremental) resistance can be large --> can get high small-signal gain (and therefore, a narrow transition region)Total current is large --> fast transitionsISUProcrociSUP(a)iSUPISUPvSUP1roc(b)(c)vSUPiSUP+_vSUP+_15EECS 105 Fall1998Lecture 15MOS Inverter with Current-Source Pull-Up■ Replace resistor with current source■ Find the voltage transfer curve graphically by superimposing iSUP vs. vOUT (load line) on top of the drain characteristicswe have a plot of iSUP vs. vSUP and we know that vOUT = VDD - vSUPtherefore, the current source iSUP vs. vOUT is a “mirrored” version of theplot of iSUP vs. vSUP CLvOUTvINvSUPiSUPiDVDD+_+_+−EECS 105 Fall1998Lecture 15Load-Line Analysis of Improved Inverter■ Voltage transfer curve with idealized current-source pull-up is much closer to that of the ideal inverter■ Question: how to implement the current source using transistors?iDvOUT = vDSVIN = VGS VDDISUP +VDDrocVOUTVIN12341234(a)(b)EECS 105 Fall1998Lecture 15p-channel MOSFET as a Current-Source Pull-Up■ Use p-channel MOSFET M2 (with well connected to the source to make VSB = 0 and source connected to the supply voltage)connect the gate to a battery VB that results in an “appropriate” value of DC current -ID2 = ID1.VDDVOUTVBVINCLID(a)VOUTIDVDD(b)IDVINVOUT(c)VOUTVIN(d)M2M15432112345. . . . . . . . . . . . .M1 Sat, M2 TriodeM1 Sat, M2 SatM1 Triode, M2 SatM1 Cutoff, M2 TriodeV+VMAX = V+VMIN+−EECS 105 Fall1998Lecture 15Voltage Transfer Curve■ In order to find the slope at VIN = VM, we note that both transistors are saturated there (near point 3) and that the small-signal models from Chapter 4 are valid■ Slope of transfer curve at VIN = VM:The transition region can be much steeper than for the resistor load, whilethe large DC drain current at VM results in short propagation delays ...what more could be desired? ■ DC power is wasted when inverter is in VOUT = VMIN state ... need a “switchable” current supply to disconnect VDD when output is lows1ropronvoutvinvgs1s2g2g1d2d1gmpvsg2 gmnvgs1 vsg2 = 0 V++−+−−vINddvOUTVMvoutvin----------gmnronrop()–==EECS 105 Fall1998Lecture 15Complementary MOS (CMOS) Inverter■ Concept: transistor switches connect output either to VDD or to ground■ Practical realization: connect input to gate of p-channel device.VIN = VDD --> VSG2 = VDD - VIN = 0 < - VTp --> cutoffVIN = 0 --> VSG2 = VDD - VIN = VDD >> - VTp --> on (triode region)■ Graphical analysis: need to find family of load lines since input is connected to gate of M2CLINPUTHIGHOUTPUTLOWINPUTLOWOUTPUTHIGHVDDVDDVDDVOUTVIN(a)(b)(c)+−CLCLEECS 105 Fall1998Lecture 15p-Channel MOSFET Characteristics■ p-channel MOS load device:VSGp = VDD - VINas VIN increases, the source-gate voltage VSGp decreases. note that the bulk connection is tied to the source (VDD), which results in a constant threshold voltage.VDD+_VIN+_VSGp+_VSDp = vSUP- IDp= iSUPEECS 105 Fall1998Lecture 15Switchable Current-Source Pull-Up* The drain characteristics are - IDp = - IDp (VSG, VSD), which can be expressed as the “switchable” pull-up’s current-voltage characteristic,iSUP = iSUP(VIN, vSUP)since iSUP = -IDp and VSG = VDD - VIN and vSUP = VSD.1234 5- IDp =VSD = vSUPiSUP - VTpEECS 105 Fall1998Lecture 15CMOS Transfer Characteristic■ plotting the p-channel pull-up on the n-channel “driver’s” drain characteristics allows us to find the input-output voltage pairs that satisfy the constraint thatIDn = - IDpVINVOUT1345IDn = −IDp−IDp = IDn(a)VDDVOUTVDDVOUTVIN(b)n-channelp-channel1 234512435VDDVDD2EECS 105 Fall1998Lecture 15CMOS Process SequenceMasks 1 and 2: n-well and activeVINVOUTGroundVDDActiven-welln-wellthick (field) oxideAAAAEECS 105 Fall1998Lecture 15CMOS Process Sequence (Cont.)Masks 3: gate polysiliconVINVOUTGroundVDDn-wellthick (field) oxidegate polysilicongate polysiliconAAAAEECS 105 Fall1998Lecture 15CMOS Process Sequence (Cont.)Mask(s) 4: Mask (clear field) for masking NMOS implant (As, donors -- for n+ source/drain regions) and is then the dark field inverse is used for masking PMOS implant (B, acceptors -- for p+ source/drain regions). As implant is heavier so polysilicon gate in n+ VINVOUTGroundVDDn-wellgate polysiliconAAAAp+p+n+p+p+n+n+EECS 105 Fall1998Lecture 15CMOS Process Sequence (Cont.)Masks 5-6: after depositing 1 µm of SiO2, etch contacts (mask 5); deposit Al metallization (mask 6) for interconnectVINVOUTGroundVDDn-wellgate
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