15 Improved Inverter Current Source Pull Up What else could be connected between the drain and VDD MOS Inverter with Current Source Pull Up Replace resistor with current source VDD iSUP vSUP iSUP iSUP vSUP ISUP vSUP roc iD CL vIN vOUT a iSUP ISUP we have a plot of iSUP vs vSUP and we know that vOUT VDD vSUP roc 1 roc Find the voltage transfer curve graphically by superimposing iSUP vs vOUT load line on top of the drain characteristics therefore the current source iSUP vs vOUT is a mirrored version of the plot of iSUP vs vSUP vSUP b c Samll signal incremental resistance can be large can get high small signal gain and therefore a narrow transition region Total current is large fast transitions EECS 105 Fall1998 Lecture 15 EECS 105 Fall1998 Lecture 15 Load Line Analysis of Improved Inverter Voltage transfer curve with idealized current source pull up is much closer to that of the ideal inverter p channel MOSFET as a Current Source Pull Up Use p channel MOSFET M2 with well connected to the source to make VSB 0 and source connected to the supply voltage connect the gate to a battery VB that results in an appropriate value of DC current ID2 ID1 iD VDD V ISUP rDD oc 4 ID VIN VGS 3 2 1 VDD ID vOUT vDS VIN a VOUT M2 VB M1 CL VOUT 1 VDD a b VOUT ID 3 VMAX V M1 Cutoff M2 Triode M1 Sat M2 Triode 1 2 4 VIN M1 Sat M2 Sat 3 b 5 4 VIN 3 4 2 VOUT 2 Question how to implement the current source using transistors VMIN 1 V VIN VOUT c EECS 105 Fall1998 Lecture 15 M1 Triode M2 Sat 5 d EECS 105 Fall1998 Lecture 15 Voltage Transfer Curve Complementary MOS CMOS Inverter In order to find the slope at VIN VM we note that both transistors are saturated there near point 3 and that the small signal models from Chapter 4 are valid Concept transistor switches connect output either to VDD or to ground VDD VDD VDD s2 vsg2 0 V vin INPUT HIGH gmpvsg2 OUTPUT LOW g1 CL gmnvgs1 a vout d1 vgs1 OUTPUT HIGH VIN rop d2 g2 INPUT LOW ron CL b CL VOUT c Practical realization connect input to gate of p channel device VIN VDD VSG2 VDD VIN 0 VTp cutoff s1 VIN 0 VSG2 VDD VIN VDD VTp on triode region Slope of transfer curve at VIN VM dv OUT d v IN VM v out gmn r on r op v in Graphical analysis need to find family of load lines since input is connected to gate of M2 The transition region can be much steeper than for the resistor load while the large DC drain current at VM results in short propagation delays what more could be desired DC power is wasted when inverter is in VOUT VMIN state need a switchable current supply to disconnect VDD when output is low EECS 105 Fall1998 Lecture 15 EECS 105 Fall1998 Lecture 15 p Channel MOSFET Characteristics p channel MOS load device Switchable Current Source Pull Up The drain characteristics are IDp IDp VSG VSD which can be expressed as the switchable pull up s current voltage characteristic VSGp VDD VIN iSUP iSUP VIN vSUP as VIN increases the source gate voltage VSGp decreases since iSUP IDp and VSG VDD VIN and vSUP VSD VDD VSGp IDp iSUP VSDp vSUP IDp iSUP VIN 1 2 3 4 5 VSD vSUP VTp note that the bulk connection is tied to the source VDD which results in a constant threshold voltage EECS 105 Fall1998 Lecture 15 EECS 105 Fall1998 Lecture 15 CMOS Transfer Characteristic CMOS Process Sequence plotting the p channel pull up on the n channel driver s drain characteristics allows us to find the input output voltage pairs that satisfy the constraint that Masks 1 and 2 n well and active VIN IDn IDp VDD VOUT VDD 1 Ground VOUT 2 n well 3 A 4 5 VDD A Active VIN IDp IDn IDn IDp A A thick field oxide n well VIN 3 3 4 1 5 VDD n channel a 2 4 2 VOUT 1 VDD 5 VOUT p channel b EECS 105 Fall1998 Lecture 15 EECS 105 Fall1998 Lecture 15 CMOS Process Sequence Cont CMOS Process Sequence Cont Mask s 4 Mask clear field for masking NMOS implant As donors for n source drain regions and is then the dark field inverse is used for masking PMOS implant B acceptors for p source drain regions As implant is heavier so polysilicon gate in n VIN Masks 3 gate polysilicon VIN VDD Ground VOUT VDD Ground VOUT gate polysilicon gate polysilicon A A A A gate polysilicon A thick field oxide A A n n well EECS 105 Fall1998 Lecture 15 p p n well n n p p A EECS 105 Fall1998 Lecture 15 CMOS Process Sequence Cont Masks 5 6 after depositing 1 m of SiO2 etch contacts mask 5 deposit Al metallization mask 6 for interconnect VIN VDD Ground VOUT gate polysilicon A A A A n p p n well n n p p A EECS 105 Fall1998 Lecture 15
View Full Document
Unlocking...