EECS 105 Spring 2005 Lecture 31 R T Howe Lecture 31 Last time Bipolar amplifier two port models Today BiCMOS voltage amplifier example of dissection technique for a complicated circuit Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 31 R T Howe Multi Stage Voltage Amplifier Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 31 R T Howe Cutting Through the Complexity Two Approaches 1 Eliminate background transistors to reduce clutter 2 Identify the signal path between the input and output Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 31 R T Howe First Approach Find I V Sources Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 31 R T Howe What s Left Voltage at base of Q2 is set by totem pole Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 31 R T Howe Second Approach Find Signal Path Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 31 R T Howe Identifying the Stages First stage or two stages CS CB cascode Second stage or two stages CD CC voltage buffer Why does this make sense for a voltage amplifier Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 31 R T Howe Find Key Two Port Parameters Output resistance of cascode Rout CS CB roc ro 2 1 g m 2 r 2 RS 2 roc Rup ro 6 1 g m 6 RS 6 Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 31 R T Howe Two Port Parameters Cont Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 31 R T Howe Output Resistance and Voltage Gain Source resistance of the CC stage is the output resistance of the CD stage small Rout Rout CC RS CC 1 1 1 1 gm4 o g m 4 g m3 o g m 4 Open circuit voltage gain Av last two stages have nearly unity gain Av g m1 o ro 2 ro 6 1 g m 6 ro 7 Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 31 R T Howe Output Swing VOUT MIN Minimum output voltage M10 M3 and Q2 are suspects M10 goes into triode when VOUT 0 5 V M3 goes into triode when VSD3 0 5 V VOUT 0 5 V 0 7 V 0 2 V Q2 goes into saturation when VCE2 0 1 V or VBC2 0 6 V VOUT VB2 VBC2 VSG3 VBE4 2 V 0 6 V 1 5 V 0 7 V VOUT 2 2 V Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 31 R T Howe Output Swing VOUT MAX Maximum output voltage Q4 M5 and M6 are suspects Q4 goes into saturation when VCE4 0 1 V VOUT 4 9 V M5 goes triode when VSD5 0 5 V VOUT 3 8 V M6 goes triode when VSD6 0 5 V VOUT VS6 0 5 V VSG3 VBE4 3 5 0 5 1 5 0 7 V 3 8 V Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 31 R T Howe Insight into the Frequency Response Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 31 R T Howe Qualitative Insight Could always do brute force open circuit time constants CS CB is a wideband stage so is the CD CC buffer Look for large RTxCx products high impedance nodes are likely candidates Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 31 R T Howe Node X CS CB is a wideband stage so is the CD CC buffer High impedance node is node X look at RTxCx Capacitance Cx Cgd6 Cdb6 C 2 Ccs2 Cgd3 CM3 Miller for CD stage M3 Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 31 R T Howe Finding the Miller Capacitance CM3 Cgs3 X CD Gain across Cgs3 AvC gs 3 RL3 RL 3 1 g m 3 RL 3 RL3 Rin4 Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 31 R T Howe Dominant Pole of Voltage Amplifier Th venin resistance for CX RTx Rout 2 Rin 3 Rout CB Rin CD RTx roc ro 2 1 g m 2 r 2 RS 2 ro 6 1 g m 6 ro 7 ro 2 o Dominant pole 1 Dept of EECS 1 RTx C x University of California Berkeley EECS 105 Spring 2005 Lecture 31 R T Howe Magnitude Bode Plot Low frequency voltage gain was found in Lecture 38 Av g m1 o ro 2 ro 6 1 g m 6 ro 7 neglect loading at output RL Rout Av j 1 Dept of EECS University of California Berkeley Gain Bandwidth product unity gain frequency
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