1Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 23Lecture 23: Active linear circuitsProf J. S. SmithDepartment of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 23 Prof. J. S. SmithContextIn the first half of the course, we reviewed linear circuit analysis, and models for the most common integrated circuit devicesResistors, capacitors, diodes, FETs and BJT’sWith today’s lecture, we will start exploring how to use transistors to make amplifiers and other active analog circuits.2Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 23 Prof. J. S. SmithReadingFor the next two lectures, and for at least a week after spring break, we will be covering chapter 8 in the text, single stage amplifiersThere is no homework assignment over spring break.Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 23 Prof. J. S. SmithLecture OutlinezParasitic capacitances in BJT Small-Signal ModelsActive Linear Circuits:zSingle stage amplifiers3Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 23 Prof. J. S. SmithBJT Small-Signal Modelbbeirvπ=1cmbe ceoigv vr=+Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 23 Prof. J. S. SmithBJT Parasitic CapacitorszEmitter-base is a forward biased junction Ædepletion capacitance:zCollector-base is a reverse biased junction Ædepletion capacitancezDue to minority charge injection into base, we have to account for the diffusion capacitance as well,,01.4jBE jBECC≈bFmCgτ=4Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 23 Prof. J. S. SmithBJT Cross SectionzCore transistor is the vertical region under the emitter contactzEverything else is “parasitic” or unwantedzLateral BJT structure is also possibleCore TransistorExternal ParasiticDepartment of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 23 Prof. J. S. SmithCore BJT ModelzGiven an ideal BJT structure, we can model most of the action with the above circuitzFor low frequencies, we can forget the capacitors zCapacitors are non-linear! MOS gate & overlap caps are linearmgvπBaseCollectorEmitterReverse biased junctionReverse biased junction &Diffusion CapacitanceFictional Resistance(no noise)5Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 23 Prof. J. S. SmithComplete Small-Signal ModelReverse biased junctions“core” BJTExternal ParasiticsReal Resistance(has noise)Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 23 Prof. J. S. SmithCircuits!zWhen the inventors of the bipolar transistor first got a working device, the first thing they did was to build an audio amplifier to prove that the transistor was actually working!6Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 23 Prof. J. S. SmithAmplifiersWe have already seen hints of what transistors can do from their small signal models:zA small voltage on the gate of a FET can change its drain currentzA small change in the current into the base of a BJT can change a large collector current.zTo make a single stage amplifier, we will need to figure out how to bias it, to provide the desired operating pointDepartment of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 23 Prof. J. S. SmithA Simple Circuit: An MOS AmplifierDSIGSVsvDRDDVGS GS svVv=+ovInput signalOutput signalSupply “Rail”7Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 23 Prof. J. S. SmithSelecting the Output Bias PointzThe bias voltage VGSis selected so that the output is mid-rail (between VDDand ground)zFor gain, the transistor is biased in saturationzConstraint on the DC drain current:zAll the resistor current flows into transistor:zMust ensure that this gives a self-consistent solution (transistor is biased in saturation)DD o DD DSRDDVVVVIRR−−==,RDSsatII=DSGSTVVV>−Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 23 Prof. J. S. SmithFinding the Input Bias VoltagezIgnoring the output impedance zTypical numbers: W = 40 µm, L = 2 µm, RD= 25k Ω, µnCox = 100 µA/V2, VTn = 1 V, VDD= 5 V2,1()2DS sat n ox GS TnWICVVLµ=−2,1()22DDDRDSsatnoxGSTnDVWII CVVRLµ== = −225V µA 1100µA 20 100 ( 1)50k V 2GSV==⋅ ⋅ −Ω2.1 ( 1)GSV=−1.32GSV=.32 2.5GS T DSVV V−=< =98Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 23 Prof. J. S. SmithApplying the Small-Signal VoltageApproach 1. Just use vGSin the equation for the total drain current iDand find voGS GS svVv=+ˆcosssvv tω=21()2ODDDDSDDDnox GSsTWvV Ri V RC V vVLµ=− =− +−Note: Neglecting charge storage effects. Ignoring device output impedance.Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 23 Prof. J. S. SmithSolving for the Output Voltage vO21()2ODDDDSDDDnox GSsTWvV Ri V RC V vVLµ=− =− +−221()12sODDDDSDDDnox GSTGS TvWvV Ri V RC V VLVVµ⎛⎞=− =− − +⎜⎟−⎝⎠DSI21sODDDDSGS TvvV RIVV⎛⎞=− +⎜⎟−⎝⎠2DDV9Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 23 Prof. J. S. SmithSmall-Signal CasezLinearize the output voltage for the s.s. casezExpand (1 + x)2= 1 + 2x + x2… last term can be dropped when x << 11vsVGSVTn–--------------------------+⎝⎠⎜⎟⎛⎞212vsVGSVTn–---- ---- ----- ---- ---- --- --vsVGSVTn–--------------------------⎝⎠⎜⎟⎛⎞2++=Neglect21sODDDDSGS TvvV RIVV⎛⎞≈− +⎜⎟−⎝⎠Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 23 Prof. J. S. SmithLinearized Output VoltageFor this case, the total output voltage is:The small-signal output voltage:212sDDODDGS TvVvVVV⎛⎞≈− +⎜⎟−⎝⎠2sDDDDOGS TvVVvVV≈−−“DC”Small-signal outputsDDovsGS TvVvAvVV≈− =−Voltage gain10Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 23 Prof. J. S. SmithPlot of Output Waveform (Gain!)Numbers: VDD/ (VGS– VT) = 5/ 0.32 = 16outputinputmVDepartment of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 23 Prof. J. S. SmithThere is a Better Way!zWhat’s missing: didn’t include device output impedance or charge storage effects (must solve non-linear differential equations…)zApproach 2. Do problem in two steps.zDC voltages and
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