Discussion Notes Voltage Sources and Current Sources Analog integrated circuits typically consist of various sub blocks connected to one another These sub blocks which are generally amplifiers use current sources to bias the transistors in such a way that we achieve the desired affect of the amplifier e g desired voltage gain current gain etc As we will discuss below transistors are used to generate these bias currents Therefore we need to set the gate voltage of the transistors in such a way that we get the desired bias current A DC voltage is needed for this Again we use transistors to generate the DC voltage Voltage Sources In this circuit M1 acts as a DC voltage source Basically Iref forces a current through M1 The other end of M1 s gate is connected to the gate of another transistor not show In a first order analysis we assume no current can flow through the gate of a transistor Therefore all of Iref flows through the drain of M1 Furthermore we know that M1 must be either in saturation or in cutoff Why Return to the current equations of an NMOS transistor Namely for saturation we need Vgs Vth Vds Vgs Vth Since the gate of M1 is tied to the same potential as the drain of M1 the first equation always holds Therefore as long as Vgs Vth the transistor is saturated and we can apply the saturation equation 2 1 W Cox Vgs Vth 1 Vds if we neglect channel length modulation 2 L which we typically do in our first order analysis of ee105 we find that Iref 2 Iref Vth W Cox L Vgs Vdsat Vth Vgs With all of the parameters in the above Vgs equation constant Vgs acts as a DC voltage source Current Sources Now that we have generated a DC voltage source we can use this to set the gate voltage of another transistor M2 and use M2 as an ideal current source How is this possible Recall an ideal current source is a circuit element whose current through it is independent of the voltage across it A MOSFET operating in saturation comes close to realizing this element If we return to the saturation equation I2 2 1 W Cox Vgs Vth 1 Vds 2 L Vgs is the DC reference voltage that we just generated and Vds is the voltage across the transistor As previously mentioned for a first order analysis we typically ignore the Vds term Therefore with this assumption a transistor operating in saturation is independent of Vds and acts like an ideal current source Although this isn t completely true it is close enough for ee105 Pictorially we have generated the following Iout Setting the value of Iout is straightforward and is done as follows 2 1 W2 Cox Vgs Vth 1 Vds 2 L2 2 W2 1 Iout Cox Vgs Vth L2 2 W2 1 2 Iref Iout Cox Vth1 Vth 2 2 W1 L2 2 Cox L1 But since quantities such as mobility oxide thickness threshold voltage etc are constant throughout a technology neglecting process variations we find I 2 Iout W2 Iref 2 L Iout and we have derived a nearly ideal current source that is a geometric W1 L1 ratio of the current source transistor and the voltage source transistor times the reference current Comments on Iref At this point you may be wondering why we don t just use Iref to bias our amplifier It turns out that we will need several different current values throughout our circuit and Iref is itself a rather complex circuit The current Iref needs to be exact i e independent of temperature variation process variation etc You will learn how to build one of these circuits if you continue on to ee140 and ee240 but for know just realize that is not feasible to have multiple Irefs and thus we must use the previous analysis to generate our bias currents Example To solidify the concepts just discussed consider the following circuit We are interested in finding the W L ratios of M1 M2 and M5 such that Iout1 40uA Iout2 100uA and Iout3 250uA given that W L r W L 4 10 2 Solution First we notice that Mr and M4 are voltage sources while M1 M2 and M5 are current sources Step 1 Solve for the dimensions of the transistors W1 L1 W2 L2 and W5 L5 W1 Iref W 1 Iout 1 Wr Iout 1 L1 Wr L1 Iref Lr Ir 40 uA 10 W1 2 2 L1 100 uA and W2 Iref W 2 Iout 2 Wr Iout 2 L 2 Wr L2 Iref Lr Ir 10 W 2 100 uA 10 2 2 L 2 100 uA What we notice here is Iout1 acts as a kind of new Iref that will set Vref2 or the gate voltage of M5 Therefore W5 Iout 1 W5 Iout 3 W 4 Iout 3 L 5 W4 L5 Iout 1 L 4 L4 W5 250 uA 10 31 25 L5 40 uA 2 If we were not given that all the transistors are in saturation we would need to check this assumption or else are equations would not hold and our above analysis would be wrong Assume the following There is a 1V drop across Iref pCox 25uA V 2 nCox 50uA V 2 Vdd 2 5V Vtp 5V Vtn 5V Step 2 Solve for the reference voltages to make sure our assumption of all devices in saturation is correct For the PMOS voltage source Mr Vr Vgr But we have a relationship for Vsgr given by Wr 1 Vsg r Vtp 2 Cox Lr 2 2 Iref Vsgr Vtp Wr Cox Lr Iref Vsr Vgr Vdd Vgr 2 Iref Vtp Wr Cox Lr 2 Iref Vtp Wr Cox Lr Therefore Vr Vgr is 2 Iref Vr Vdd Vtp 1 27V Wr Cox Lr For the NMOS voltage source M4 2 Iout1 Vgs 4 Vtn W4 nCox L4 and Vref 2 Vg 4 but Vg 4 Vs 4 2 Iout1 Vtn 0 W4 nCox L4 Thus Vref 4 Vgs 4 1 07V Know we can check that Mr M1 and M4 are saturated For Mr and M4 we simply need to check the condition Vgs Vt since the gate and drain are at the same potential For Mr Vgs 1 27 Vdd 1 27 2 5 1 23V 5V For M4 Vgs 1 07V 5V so M4 is saturated so Mr is saturated For M1 we must check the condition that Vgs Vtp Vds and Vgs Vtp Thus Vgs Vr Vdd 1 27 2 5V 1 23V Vds Vref2 Vdd 1 07 2 5 1 43V So 1 23V 5V and 1 23V 5V 1 43V so M1 is saturated For M5 and M2 we would need to know there drain voltages which depend on the amplifiers they are connected to So we don t have enough information
View Full Document
Unlocking...