R. T. HoweEECS 105 Spring 2005 Lecture 10Dept. of EECSUniversity of California, BerkeleyLecture 10• Last time:– MOS Sample and Hold Circuit: linear and non-linear analysis• Today :– Introduction to amplifiers: a common-source MOS stageR. T. HoweEECS 105 Spring 2005 Lecture 10Dept. of EECSUniversity of California, BerkeleyAn MOS AmplifierDictionary definition:amplify =R. T. HoweEECS 105 Spring 2005 Lecture 10Dept. of EECSUniversity of California, BerkeleySweep Input Voltage vIN-VSUP+VSUP-VSUP+ VTnMOSFET is saturated Æhigh slopeMOSFET is triode Ælow slopevIN= vG–(-VSUP)_-VSUPR. T. HoweEECS 105 Spring 2005 Lecture 10Dept. of EECSUniversity of California, BerkeleySelecting the Output Bias PointVBIASis selected so that VOUTis centered between +VSUPand –VSUP(why?)VOUT= 0 V ... NOT vOUT= 0 V!Constraint on the DC drain current: IRD= (VSUP- VOUT) / RD= VSUP / RDIRD= ID = ID,SAT... verify that MOSFET is saturated after finding VBIASR. T. HoweEECS 105 Spring 2005 Lecture 10Dept. of EECSUniversity of California, BerkeleyFinding the Input Bias VoltageHand calculation: use ID,SAT2,)()2/(TnGSoxnSATDVVCLWI −=µTypical numbers: W = 40 µm, L = 2 µm, RD= 25 k ΩµnCox= 100 µA/V2, VTn= 1 V, VSUP= 2.5 V==DSUPRDRVI2,)1(10010 −⋅⋅=GSSATDVIR. T. HoweEECS 105 Spring 2005 Lecture 10Dept. of EECSUniversity of California, BerkeleyApplying the Small-Signal VoltagevINVBIASvs+=vst() vˆsωt()cos=Approach 1. Just use vINin the equation for the total drain current iDand find vOUTvOUTVSUPRDiD– VSUPRDµnCox()W2L------VGSvsVTn–+()2–≅=][)(SUPsBIASSUPINGSVvVVvv++=−−=Result:R. T. HoweEECS 105 Spring 2005 Lecture 10Dept. of EECSUniversity of California, BerkeleySolving for the Output Voltage vOUTvOUTVSUPRDµnCox()W2L------VGSVTn–()21vsVGSVTn–()------------------------------+2–=IDvOUTVSUPRDID1vsVGSVTn–()------------------------------+2–=VSUPR. T. HoweEECS 105 Spring 2005 Lecture 10Dept. of EECSUniversity of California, BerkeleySmall-Signal CaseExpand (1 + x)2= 1 + 2x + x2 … last term can be dropped when x << 11vsVGSVTn–--------------------------+212vsVGSVTn–--------------------------vsVGSVTn–--------------------------2++=Linearize the output voltage for the s.s. caseR. T. HoweEECS 105 Spring 2005 Lecture 10Dept. of EECSUniversity of California, BerkeleyLinearized Output VoltageFor this case, the total output voltage is vOUTVSUPRDID12vsVGSVTn–()------------------------------+–≅ VSUPVSUP–2RDIDvsVGSVTn–()------------------------------–=The average output voltage VOUT= 0 V so the total output voltage is the small-signal voltage in this special case:vOUTvout2RDIDVGSVTn–()------------------------------ vs–2VSUPVGSVTn–()------------------------------ vs– Avvs== = =R. T. HoweEECS 105 Spring 2005 Lecture 10Dept. of EECSUniversity of California, BerkeleyPlot of Output WaveformNumbers: 2 IDRD / (VGS– VTn) = (2 x 2.5) / 0.31 = 16.1R. T. HoweEECS 105 Spring 2005 Lecture 10Dept. of EECSUniversity of California, BerkeleyIs there a Better Way?What’s missing: no inclusion of fudge factor term or of charge storage effectsApproach 2. Do problem in two steps.1. DC voltages and currents (ignore small signals sources):set bias point of the MOSFET ... we had to do this to pick VBIASalready2. Substitute the small-signal model of the MOSFET andthe small-signal models of the other circuit elements
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