EECS 105 Spring 2005 Lecture 10 R T Howe Lecture 10 Last time MOS Sample and Hold Circuit linear and nonlinear analysis Today Introduction to amplifiers a common source MOS stage Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 10 R T Howe An MOS Amplifier Dictionary definition amplify Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 10 R T Howe Sweep Input Voltage vIN VSUP MOSFET is saturated high slope VSUP VTn vIN vG VSUP VSUP MOSFET is triode low slope VSUP Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 10 R T Howe Selecting the Output Bias Point VBIAS is selected so that VOUT is centered between VSUP and VSUP why VOUT 0 V NOT vOUT 0 V Constraint on the DC drain current IRD VSUP VOUT RD VSUP RD Dept of EECS IRD ID ID SAT verify that MOSFET is saturated after finding VBIAS University of California Berkeley EECS 105 Spring 2005 Lecture 10 R T Howe Finding the Input Bias Voltage Hand calculation use ID SAT I D SAT W 2 L n Cox VGS VTn 2 Typical numbers W 40 m L 2 m RD 25 k nCox 100 A V2 VTn 1 V VSUP 2 5 V I RD Dept of EECS VSUP 2 I D SAT 10 100 VGS 1 RD University of California Berkeley EECS 105 Spring 2005 Lecture 10 R T Howe Applying the Small Signal Voltage Approach 1 Just use vIN in the equation for the total drain current iD and find vOUT v IN V BIAS v s vGS v IN VSUP VBIAS vs VSUP vs t v s cos t Result 2 W v OUT V SUP R D i D V SUP R D n C ox V GS vs V Tn 2L Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 10 R T Howe Solving for the Output Voltage vOUT 2 v s W V V 2 1 v OUT V SUP R D n C ox Tn 2L GS V V GS Tn ID 2 vs vOUT VSUP R D ID 1 VGS VTn VSUP Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 10 R T Howe Small Signal Case Linearize the output voltage for the s s case Expand 1 x 2 1 2x x2 last term can be dropped when x 1 2 2 v 2v v s s s 1 1 V V V V GS Tn GS Tn V GS V Tn Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 10 R T Howe Linearized Output Voltage For this case the total output voltage is 2R D I D v 2v s s v OUT V S UP R D I D 1 V S UP V SUP V GS V Tn V GS V Tn The average output voltage VOUT 0 V so the total output voltage is the small signal voltage in this special case 2V SUP 2R D I D v OUT v ou t v s v s A v v s V GS V Tn V GS V Tn Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 10 R T Howe Plot of Output Waveform Numbers 2 IDRD VGS VTn 2 x 2 5 0 31 16 1 Dept of EECS University of California Berkeley EECS 105 Spring 2005 Lecture 10 R T Howe Is there a Better Way What s missing no inclusion of fudge factor term or of charge storage effects Approach 2 Do problem in two steps 1 DC voltages and currents ignore small signals sources set bias point of the MOSFET we had to do this to pick VBIAS already 2 Substitute the small signal model of the MOSFET and the small signal models of the other circuit elements Dept of EECS University of California Berkeley
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