Berkeley ELENG 105 - Lecture 33 (12 pages)

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Lecture 33



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Lecture 33

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Pages:
12
School:
University of California, Berkeley
Course:
Eleng 105 - Microelectronic Devices and Circuits
Microelectronic Devices and Circuits Documents

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EECS 105 Spring 2002 Lecture 33 R T Howe Lecture 33 Last time Frequency response of voltage and current buffers Voltage Current sources using MOS transistors Today Improved current sources Current mirrors Dept of EECS University of California at Berkeley EECS 105 Spring 2002 Lecture 33 R T Howe Equivalent Circuit for I Source Find the DC current for gray circle equivalent circuit I OUT Dept of EECS nCox W 2 VREF VTn L 2 2 Substitute for VREF University of California at Berkeley EECS 105 Spring 2002 Lecture 33 R T Howe Small Signal Resistance of I Source Dept of EECS University of California at Berkeley EECS 105 Spring 2002 Lecture 33 R T Howe Improved Current Sources Goal increase roc Approach look at amplifier output resistance results to see topologies that boost resistance Dept of EECS University of California at Berkeley EECS 105 Spring 2002 Lecture 33 R T Howe Cascode or Stacked Current Source Insight VGS2 constant AND VDS2 constant Small Signal Resistance roc Dept of EECS University of California at Berkeley EECS 105 Spring 2002 Lecture 33 R T Howe Drawback of Cascode I Source Minimum output voltage for all transistors saturated VOUT MIN VDS 4 SAT VS 4 VDS 4 SAT VGS 2 iOUT vOUT Dept of EECS University of California at Berkeley EECS 105 Spring 2002 Lecture 33 R T Howe Current Sinks and Sources Sink output current goes to ground Dept of EECS Source output current comes from voltage supply University of California at Berkeley EECS 105 Spring 2002 Lecture 33 Current Mirrors R T Howe Idea we only need one reference current to set up all the current sources and sinks needed for a multistage amplifier Dept of EECS University of California at Berkeley EECS 105 Spring 2002 Lecture 33 R T Howe Multistage Amplifiers Necessary to meet typical specifications for any of the 4 types We have 2 flavors NMOS PMOS of CS CG and CD and the npn versions of CE CB and CC for a BiCMOS process What are the constraints 1 Input output resistance matching 2 DC coupling no passive elements



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