Lecture 18: Bipolar Single Stage AmplifiersLecture OutlineBipolar AmplifiersSmall-Signal Two-Port ModelCommon-Base AmplifierCB Input ResistanceCB Output ResistanceOutput Impedance DetailsOutput Impedance CalculationCommon-Base Two-Port ModelCommon-Collector AmplifierCommon-Collector Input ResistanceCommon-Collector Output ResistanceCommon-Collector Output Res. (cont)Common-Collector Voltage GainCommon-Collector Two-Port ModelSlide 17Typical “Discrete” BiasingGain for “Discrete” DesignDepartment of EECS University of California, BerkeleyEECS 105 Fall 2003, Lecture 18Lecture 18: Bipolar Single Stage AmplifiersProf. NiknejadDepartment of EECS University of California, BerkeleyEECS 105 Fall 2003, Lecture 18 Prof. A. NiknejadLecture OutlineBJT AmpsBJT BiasingCommon Emitter AmpCommon Base AmpCommon Collector Amp –AKA Emitter Followerβ Multiplier ConceptEmitter DegenerationDepartment of EECS University of California, BerkeleyEECS 105 Fall 2003, Lecture 18 Prof. A. NiknejadBipolar AmplifiersCommon-emitter amplifier: Biasing: adjustVBIAS = VBE sothat IC = ISUP.Department of EECS University of California, BerkeleyEECS 105 Fall 2003, Lecture 18 Prof. A. NiknejadSmall-Signal Two-Port ModelParameters: (IC = 1 mA, β =100, VA = 3V)oc3V|| || 3k||r 3k1mAout o oc ocR r r r= = = �25mV100 2.5k1mAinmR rgpb= = = = W1mA 1S 40mS25mV 25m mG g= = = =Department of EECS University of California, BerkeleyEECS 105 Fall 2003, Lecture 18 Prof. A. NiknejadCommon-Base AmplifierTo find IBIAS, note that IBIAS = IE = - (1/F)ICCommon-base currentgain Ai = - FDepartment of EECS University of California, BerkeleyEECS 105 Fall 2003, Lecture 18 Prof. A. NiknejadCB Input ResistanceSumming currents at the input node:( ) 0t m o t ovi g v v v grppp+ + + - =small1t m ti g vrp� �= +� �� �111 1t min m mt mv gR g gi r gpb--� �� �= = + = + �� �� �� �� �25mV251mA= = WDepartment of EECS University of California, BerkeleyEECS 105 Fall 2003, Lecture 18 Prof. A. NiknejadCB Output Resistancenotepolarityput roc back inafter finding vt / itSame topology as CG amplifier, but with r || RS rather than RS( )|| 1 ( ||out oc o m SR r r g r Rp� �= +� �( )|| 1out oc o mR r r g rp� �= +� �SR rp>>( )|| 1out oc oR r r b= +Department of EECS University of California, BerkeleyEECS 105 Fall 2003, Lecture 18 Prof. A. NiknejadOutput Impedance DetailsFirst draw small signal equivalent circuit with transistor and simplify as much as possibleThen (if needed) add the small signal equivalent circuitIf frequency is low, get rid of caps!Department of EECS University of California, BerkeleyEECS 105 Fall 2003, Lecture 18 Prof. A. NiknejadOutput Impedance Calculationtv+-tirpvp+-SRmg vpor( )tt mov vi g vrpp- -= +( || )t Sv i R rp p=-||( || )t St m t S to ov R ri g i R r ir rpp-=- + +||1 ( || )S tt m So oR r vi g R rr rpp� �+ + =� �� �Department of EECS University of California, BerkeleyEECS 105 Fall 2003, Lecture 18 Prof. A. NiknejadCommon-Base Two-Port ModelWhy did we consider it a current amp?Current Amp :•Unity Current Gain (-1)•Small Input Impedance•Large (huge!) Output ImpedanceDepartment of EECS University of California, BerkeleyEECS 105 Fall 2003, Lecture 18 Prof. A. NiknejadCommon-Collector AmplifierDC Bias:output is one“VBE drop” downfrom input“Emitter Follower”Department of EECS University of California, BerkeleyEECS 105 Fall 2003, Lecture 18 Prof. A. NiknejadCommon-Collector Input Resistance( 1) ( || || )t t t L o ocv i r i R r rpb= + +( 1)( || || )in L o ocR r R r rpb= + +( 1)in LR r Rpb� + +Department of EECS University of California, BerkeleyEECS 105 Fall 2003, Lecture 18 Prof. A. NiknejadCommon-Collector Output ResistanceDivider between vt and v :1 1( || ) 0t m t o oci g v v r v r rp p p- -+ + - =tSrv vr Rppp=+( )1 1( || )t t m t o ocSri v g r v r rr Rppp- -� �= + +� �+� �Department of EECS University of California, BerkeleyEECS 105 Fall 2003, Lecture 18 Prof. A. NiknejadCommon-Collector Output Res. (cont)Looking into base of emitter follower: load impedance larger by factor β+1Looking into emitter of follower: “source” impedance smaller by factor β+1( )1 1( || )t t m t o ocSri v g r v r rr Rppp- -� �= + +� �+� �( )11t t mSi v g rr Rpp� �= +� �+� �1t Souttv r RRipb+= =+Department of EECS University of California, BerkeleyEECS 105 Fall 2003, Lecture 18 Prof. A. NiknejadCommon-Collector Voltage GainKCL at the output node: note v = vt - vout( )11||out oc o mv r r g v v rp p p--= +( ) ( )11|| ( )out oc o m t outv r r g r v vp--= + -( )()( )11 1||out oc o m m tv r r g r g r vp p-- -+ + = +out tv v=Department of EECS University of California, BerkeleyEECS 105 Fall 2003, Lecture 18 Prof. A. NiknejadCommon-Collector Two-Port Modeltypo: RLVoltage Amp :•Unity Voltage Gain (+1)•Large Input Impedance•Small Output ImpedanceDepartment of EECS University of California, BerkeleyEECS 105 Fall 2003, Lecture 18 Prof. A. NiknejadSummary of Two-Port ParametersDepartment of EECS University of California, BerkeleyEECS 105 Fall 2003, Lecture 18 Prof. A. NiknejadTypical “Discrete” BiasingA good biasing scheme must be relatively insensitive to transistor parameters (vary with process and temperature)In this scheme, the base current is given by:The emitter current:11 2B CCRV VR R=+1,1 2/E CC BE on ERI V V RR R� �� -� �+� �1R2RCRERCCVDepartment of EECS University of California, BerkeleyEECS 105 Fall 2003, Lecture 18 Prof. A. NiknejadGain for “Discrete” DesignLet’s derive it by intuitionInput impedance can be made large enough by designDevice acts like follower, emitter=baseThis signal generates a collector current1R2RCRERsv( 1)( )( 1)in EER r RRpbb� + +� +2 1 2( 1) || ||in ER R R Rb� +Can be made large to coupleAll of source to input (even with RS)~sv/s Ev R~ /s C Ev R
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