Experiment 4 MOS Device Characterization W T Yeung and R T Howe UC Berkeley EE 105 Fall 2004 1 0 Objective In this experiment you will find the device parameters for an n channel MOSFET From the parameters you will reproduce its I V characteristics and compare them to SPICE The characteristics will be compared to the SPICE level 1 model We will also compare your data with data from the HP 4155 analyzer The key concepts you should learn in this lab are determining which region of operation the MOSFET is in depending on the values of VGS and VDS application of correct equations for ID depending on the region of operation extraction of basic SPICE parameters from experimental measurements 2 0 Prelab 1 Review lecture discussion notes relating to MOSFET physics regions of operation 2 Prepare a SPICE deck for the circuit in Fig 1 Let VDS range from 0 5 V in 0 1V increments and let VGS range from 0 5V in 1V increments Print a plot of ID vs VDS with VGS as a parameter Using this plot explain how one would obtain the parameters VTOn Kn nCox and n Use the following SPICE parameters for getting started note SPICE uses Kp for Kn VTOn 1 V Kp 100 A V2 n 0 05 V 1 1 of 11 Procedure FIGURE 1 Circuit for SPICE simulation as described in Prelab procedure 2 W L 46 5 m 1 5 m VDS ID VDS VGS 3 Prepare a SPICE deck for the circuit in Fig 2 Print a plot of ID vs VGS Let VGS range from 0 to 5V Using this plot explain how one would obtain the parameters VTO and Kn nCox Use the same SPICE parameters as procedure 2 FIGURE 2 Circuit for SPICE simulation as described in prelab procedure 3 VDS ID VGS VDS 50 mV 3 0 Procedure 1 Check out 3 banana cables and a Lab Chip 1 chip from your lab TA 2 Place chip Lab Chip 1 into the parameter analyzer test fixture or Lab Chip socket on your breadboard If using the breadboard DO NOT place your Lab Chip in any other place besides in the socket at the center of the board The pinouts for NMOS1 are as follows drain PIN3 gate PIN4 source PIN 5 In addition to providing connections to the three pins mentioned above connect PIN 14 to common to provide a ground reference for the chip Figure 3 shows how SMUs are connected to the pins of the chip Figure 4 shows how the SMUs are being used in the experiment 2 of 11 Experiment 4 MOS Device Characterization Procedure FIGURE 3 4155 Test Fixture showing SMU1 being connected to pin 2 of a 28pin chip SMU1 1 2 3 4 7 8 5 6 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FIGURE 4 25 26 27 28 Circuit to gather data for ID vs VDS plot Note SMUs in dashed boxes VDS V ID A VDS VGS Drain Pin3 Gate Pin4 Source Pin5 Common Pin14 0V 3 Using the Metrics program see Lab 3 step the gate voltage from 0 to 5V and sweep V DS from 0 to 5 V to obtain a drain current versus drain source voltage plot similar to that displayed in Figure 5 4 Determine n from the plots obtained in part 3 above see appendix for assistance on this matter Experiment 4 MOS Device Characterization 3 of 11 Procedure 5 Comment on the shape of the graphs obtained in part 3 In particular how does VDS SAT compare with theory How does ID SAT compare with theory Your comparisons should be quantitative 6 Obtain print outs of your data FIGURE 5 Sample ID vs VDS characteristic of NMOS ID VDS FIGURE 6 Sample ID vs VDS characteristic showing a best fit line to find n 4 of 11 Experiment 4 MOS Device Characterization Procedure 3 1 Finding VTOn and Kn in the Triode Region 1 Using the Metrics program configure the SMUs to provide a setup similar to that displayed in Figure 7 More specifically make the drain source voltage a constant 50mV and sweep the gate source voltage from 0 to 5V to obtain a plot of ID vs VGS 2 The MOSFET is in the triode region for VGS VTOn 50 mV write the equation for ID that corresponds to this region of operation FIGURE 7 Circuit to gather data for ID vs VGS plot Note SMUs in dashed boxes VDS V ID VGS A Drain Pin3 Gate Pin4 VDS 50mV Source Pin5 Common Pin14 0V 3 From your plot of ID vs VGS in the triode region find the best fit line and estimate both VTn and the Kn parameter Use the W and L values from the prelab in your calculations 4 Obtain print outs of your data 3 2 Finding VTOn and Kn in the Saturation Region 1 Using the Metrics program configure the SMUs to provide a setup similar to that displayed in Figure 8 More specifically make the drain source voltage a constant 5V and sweep the gate source voltage from 0 to 5V to obtain a plot of ID vs VGS 2 The MOSFET is in the saturation region for VGS VTOn 5 V write the equation for ID that corresponds to this region of operation 3 Find the best fit line for the plot of ID1 2 vs VGS in the saturation region as shown in Fig 10 Use the slope and intercept of the best fit line to estimate both VTn and the Kn parameter 4 Obtain print outs of your data Experiment 4 MOS Device Characterization 5 of 11 Procedure FIGURE 8 Circuit to gather data for ID 1 2 vs VGS plot Note SMUs in dashed boxes VDS V FIGURE 9 ID A VDS 5 V VGS Drain Pin3 Gate Pin4 Source Pin5 Common Pin14 0V Sample ID vs VGS characteristic of NMOS ID VGS 6 of 11 Experiment 4 MOS Device Characterization Optional Experiments Extra Credit FIGURE 10 Sample ID 1 2 vs VGS characteristic showing a best fit line to find VTo and Kn ID 1 2 VGS 3 3 Comparison with SPICE 1 Fill in the value of VTO Kn and n in the data sheet in the appendix You will need to refer to these values in future labs 2 The values you extracted will be used in SPICE to model the NMOS Using the SPICE decks that you have done for prelab replace the values of VTo Kn and n with the ones you just found note that Kn is defined as Kp in SPICE 3 Obtain plots of ID vs VDS and ID vs VGS as you did in prelab 4 Compare the experimental plots with the plots you generated in SPICE How do the values of ID SAT compare for a given VDS SAT Note that the Level 1 SPICE model is not adequate for accurate modeling of devices with channel lengths shorter than around 2 m 4 0 Optional Experiments Extra Credit 4 1 PMOS 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