EE105 Fall 2005 Microelectronic Devices and Circuits Lecture 22 Frequency Response of Common Drain Common Source Amplifiers Multistage Amplifiers Announcements Homework 10 due on Tuesday Lab 8 this week Friday is a University holiday no lab discussion Friday s lab 8 on November 18 No new lab next week Midterm 2 next Thursday Nov 17 6 30 8pm Sibley Review session on Tuesday Nov 15 6 30 8pm 277 Cory Reading Chapter 9 9 1 9 3 9 5 2 1 Lecture Material Last lecture Time constants This lecture Common drain common gate frequency response Multistage amplifiers 3 Gain Bandwidth Product Common source amp result from Miller Cgd p1 1 RS Cgs 1 g m Rout Low frequency gain v Avo out g m Rout vs 4 2 Gain Bandwidth Product Considering only the first pole assuming zero and 2nd pole are at much higher frequencies Avo Av j dB Av j Avo p1 Avo A vo 1 j p1 p1 Av j 1 Avo p1 5 Gain Bandwidth Product For common source amplifier Avo p1 g m Rout Cgd RSCgs RS 1 g m Rout Special case RS RL ro roc Avo p1 g m RL T RS Cgs g m RLCgd not that great 6 3 Common Drain Amplifier VDD vOUT Rs vs VGS ICS RL VSS 7 Two Port CD Model with Capacitors Ignore gmb Find Miller capacitor for Cgs note that the gate source capacitor is between the input and output 8 4 Voltage Gain AvCgs Across Cgs AvC gs Rout 1 RL Rout This gain is independent of Cgs C in Cgd CM Cgd 1 AvCgs Cgs C in Cgd 1 Cgs 1 g m RL C in Cgd 9 Bandwidth of CD Amplifier Input low pass filter s 3 dB frequency Cgs p 1 RS Cgd 1 g R m L Substitute favorable values of RS RL RS 1 g m RL 1 g m Cgd Cgd g m p 1 1 g m Cgd 1 BIG p g m Cgd T Model not valid at these high frequencies 10 5 Bandwidth of the Common Gate Amplifier 11 Two Port CG Model with Capacitors Cgd vout Cgs vgs gmvgs ro RL roc Rs vs No Miller transformed capacitor Unity gain frequency is on the order of T for small RL 12 6 Summary of Single Stage Amplifiers CS suffers from Miller magnified capacitor for highgain case CD Miller transformation nulled capacitor wideband stage CG no Millerized capacitor wideband stage for low load resistance 13 Multistage Amplifiers Necessary to meet typical specifications for any of the 4 types We have 2 flavors NMOS PMOS of each CS CG and CD What are the constraints 1 Input output resistance matching 2 DC coupling no passive elements to block the signal why not 14 7 Start Two Stage Voltage Amplifier Use two port models to explore whether the combination works CS2 CS1 Results Rin Rin1 Rout Rout2 Av 15 Bandwidth of a Cascaded Stages Assume identical stages same dominant pole p A0 ATOT j 1 j p A0 ATOT 1 BW p 2 BW 21 n 1 p N N A0 1 2 1 2 p N N 2 BW 0 64 p N 3 BW 0 51 p 16 8 Using CMOS Stages CS2 CS1 CD3 Input resistance Voltage gain 2 port parameter Output resistance 17 Multistage Current Buffers Are two cascaded common gate stages better than one CG1 CG2 Input resistance Rin Rin1 18 9 Summary of Cascaded Amplifiers General goals 1 Boost the gain parameter except for buffers 2 Optimize the input and output resistances Rin Voltage Current Transconductance Transresistance Rout 19 Second Design Issue DC Coupling Constraint large inductors and capacitors are not available Output of one stage is directly connected to the input of the next stage must consider DC levels why VDD ISUP1 ISUP2 vOUT M1 M2 20 10 21 22 11 Alternate CS CS Cascade Use a PMOS CS Stage VDD ISUP1 M2 M1 vs vOUT ISUP2 VS 23 Complete Amplifier 24 12
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