1EE105 - Fall 2005Microelectronic Devices and CircuitsLecture 22Frequency Response of Common Drain/Common Source AmplifiersMultistage Amplifiers2AnnouncementsHomework 10 due on TuesdayLab 8 this weekFriday is a University holiday (no lab/discussion)Friday’s lab 8 on November 18No new lab next weekMidterm 2 next Thursday, Nov. 17, 6:30-8pm, SibleyReview session on Tuesday, Nov. 15, 6:30-8pm, 277 CoryReading: Chapter 9 (9.1, 9.3, 9.5)23Lecture MaterialLast lectureTime constantsThis lectureCommon drain, common gate frequency responseMultistage amplifiers4Gain-Bandwidth ProductCommon source amp - result from Miller:Low-frequency gain:outmsoutvoRgvvA′−==() ( ){}gdoutmgsSpCRgCR′++≈ω−11135Gain-Bandwidth ProductConsidering only the first pole(assuming zero and 2ndpole are at much higher frequencies):()1*=ωjAvω()dBvjAωvoA*ω()ωω=ωω≈ωω+≈ω1111pvopvopvovAAjAjA1*pvoA ω=ωÆ6Gain-Bandwidth ProductFor common-source amplifier:()gdoutmSgsSoutmpvoCRgRCRRgA′++′=ω11Special case: RS≈ RL< ro, rocTgdLmgsSLmpvoCRgCRRgA ω<<+≈ω)(1not that great!47Common-Drain AmplifierVDDRsRL+vOUT+vsVGS-VSSICS8Two-Port CD Model with CapacitorsIgnore gmbFind Miller capacitor for Cgs-- note that the gate-source capacitor isbetween the input and output59Voltage Gain AvCgsAcross CgsThis gain is independent of CgsgsgsvCgdMgdinCACCCC )1(−+=+=1≈+=outLoutgsvCRRRAgsLmgdinCRgCC++=11gdinCC≈10Bandwidth of CD AmplifierInput low-pass filter’s –3 dB frequency:⎟⎟⎠⎞⎜⎜⎝⎛++=ω−LmgsgdSpRgCCR11Substitute favorable values of RS, RL:mSgR /1≈mLgR /1>>()mgdgdgdmpgCBIGCCg /1/11≈⎟⎟⎠⎞⎜⎜⎝⎛++≈ω−Model not valid at these high frequenciesTgdmpCgω>≈ω /611Bandwidth of the Common-Gate Amplifier12Two-Port CG Model with CapacitorsNo Miller-transformed capacitor!Unity-gain frequency is on the order of ωTfor small RL+voutvsrovgs+CgsCgdgmvgsRsRL||roc713Summary of Single-Stage AmplifiersCS: suffers from Miller-magnified capacitor for high-gain caseCD: Miller transformation Æ nulled capacitor Æ“wideband stage”CG: no “Millerized” capacitor Æ wideband stage (for low load resistance)14Multistage AmplifiersNecessary to meet typical specifications for any of the 4 typesWe have 2 flavors (NMOS, PMOS) of each CS, CG, and CDWhat are the constraints?1. Input/output resistance matching2. DC coupling (no passive elements to block the signal)… why not?815Start: Two-Stage Voltage Amplifier• Use two-port models to explore whether the combination “works”CS1CS2Results: Rin= Rin1, Rout= Rout2, Av=16Bandwidth of a Cascaded StagesAssume identical stages, same dominant pole, ωpNpTOTjAjA⎟⎟⎠⎞⎜⎜⎝⎛ωω+=ω1)(0()NpA⎟⎟⎟⎠⎞⎜⎜⎜⎝⎛ωω+=2012112/1−=ωωnpBW()NpBWTOTAA⎟⎟⎟⎠⎞⎜⎜⎜⎝⎛ωω+=201N = 2 ωBW= 0.64ωpN = 3 ωBW= 0.51ωp917Using CMOS StagesCS1CS2CD3Output resistance: Voltage gain (2-port parameter): Input resistance: 18Multistage Current Buffers CG1 CG2Are two cascaded common-gate stages better than one?Input resistance: Rin= Rin11019Summary of Cascaded AmplifiersGeneral goals:1. Boost the gain parameter (except for buffers)2. Optimize the input and output resistancesRinRoutVoltage:Current:Transconductance:Transresistance:20Second Design Issue: DC CouplingConstraint: large inductors and capacitors are not available Output of one stage is directly connected to the inputof the next stage Æ must consider DC levels … why? VDDISUP1+vOUTM1M2ISUP21121221223Alternate CS-CS CascadeUse a PMOS CS Stage:VDDISUP1+vsvOUTVSM1M2ISUP224Complete
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