Chapter 5 Bipolar Amplifiers EE105 Spring 2007 Microelectronic Devices and Circuits 5 1 5 2 5 3 5 4 General Considerations Operating Point Analysis and Design Bipolar Amplifier Topologies Summary and Additional Examples Lecture 11 Bipolar Amplifiers Part 1 2 Bipolar Amplifiers Voltage Amplifier 3 In an ideal voltage amplifier the input impedance is infinite and the output impedance zero But in reality input or output impedances depart from their ideal values 4 Input Output Impedances Rx Input Impedance Example I Vx ix vx r ix The figure above shows the techniques of measuring input and output impedances When calculating input output impedance small signal analysis is assumed 5 Impedance at a Node 6 Impedance at Collector Rout ro When calculating I O impedances at a port we usually ground one terminal while applying the test source to the other terminal of interest 7 With Early effect the impedance seen at the collector is equal to the intrinsic output impedance of the transistor if emitter is grounded 8 Impedance at Emitter Three Master Rules of Transistor Impedances vx 1 ix g 1 m r 1 Rout gm VA The impedance seen at the emitter of a transistor is approximately equal to one over its transconductance if the base is grounded Rule 1 looking into the base the impedance is r if emitter is ac grounded Rule 2 looking into the collector the impedance is ro if emitter is ac grounded Rule 3 looking into the emitter the impedance is 1 gm if base is ac grounded and Early effect is neglected 9 Biasing of BJT Transistors and circuits must be biased because 1 transistors must operate in the active region 2 their small signal parameters depend on the bias conditions 10 DC Analysis vs Small Signal Analysis First DC analysis is performed to determine operating point and obtain small signal parameters Second sources are set to zero and small signal model is used 11 12 Notation Simplification Example of Bad Biasing The microphone is connected to the amplifier in an attempt to amplify the small output signal of the microphone Hereafter the battery that supplies power to the circuit is replaced by a horizontal bar labeled Vcc and input signal is simplified as one node called Vin 13 Another Example of Bad Biasing Unfortunately there s no DC bias current running through the transistor to set the transconductance 14 Biasing with Base Resistor VCC VBE RB V VBE I C CC RB IB The base of the amplifier is connected to Vcc trying to establish a DC bias Unfortunately the output signal produced by the microphone is shorted to the power supply Assuming a constant value for VBE one can solve for both IB and IC and determine the terminal voltages of the transistor However bias point is sensitive to variations 15 16 Improved Biasing Resistive Divider Accounting for Base Current R2 VCC R1 R2 R2 VCC I C I S exp R1 R2 VT VX V I R I C I S exp Thev B Thev VT Using resistor divider to set VBE it is possible to produce an IC that is relatively independent of if base current is small 17 Emitter Degeneration Biasing With proper ratio of R1 and R2 IC can be insensitive to however its exponential dependence on resistor deviations makes it less useful 18 Design Procedure Choose an IC to provide the necessary small signal parameters gm r etc Considering the variations of R1 R2 and VBE choose a value for VRE With VRE chosen and VBE calculated Vx can be determined Select R1 and R2 to provide Vx The presence of RE helps to absorb the error in VX so VBE stays relatively constant This bias technique is less sensitive to I1 IB and VBE variations 19 20 Self Biasing Technique Self Biasing Design Guidelines 1 RC RB 2 VBE VCC VBE This bias technique utilizes the collector voltage to provide the necessary Vx and IB One important characteristic of this technique is that collector has a higher potential than the base thus guaranteeing active operation of the transistor 1 provides insensitivity to 2 provides insensitivity to variation in VBE 21 Summary of Biasing Techniques 22 PNP Biasing Techniques Same principles that apply to NPN biasing also apply to PNP biasing with only polarity modifications 23 24 Possible Bipolar Amplifier Topologies Study of Common Emitter Topology Analysis of CE Core Inclusion of Early Effect Emitter Degeneration Inclusion of Early Effect CE Stage with Biasing Three possible ways to apply an input to an amplifier and three possible ways to sense its output However in reality only three of six input output combinations are useful 25 Common Emitter Topology 26 Small Signal of CE Amplifier Av vout vin vout g m v g m vin RC Av g m RC 27 28 Limitation on CE Voltage Gain Tradeoff between Voltage Gain and Headroom I C RC VT V Av RC VT V VBE Av CC VT Av Since gm can be written as IC VT the CE voltage gain can be written as the ratio of VRC and VT VRC is the potential difference between VCC and VCE and VCE cannot go below VBE in order for the transistor to be in active region 29 I O Impedances of CE Stage Rin vX r iX Rout 30 CE Stage Trade offs vX RC iX When measuring output impedance the input port has to be grounded so that Vin 0 31 32 Inclusion of Early Effect Intrinsic Gain Av g m rO V Av A VT Av g m RC rO Rout RC rO As RC goes to infinity the voltage gain reaches the product of gm and rO which represents the maximum voltage gain the amplifier can have The intrinsic gain is independent of the bias current Early effect will lower the gain of the CE amplifier as it appears in parallel with RC 33 Current Gain 34 Emitter Degeneration iout iin AI CE AI Another parameter of the amplifier is the current gain which is defined as the ratio of current delivered to the load to the current flowing into the input By inserting a resistor in series with the emitter we degenerate the CE stage This topology will decrease the gain of the amplifier but improve other aspects such as linearity and input impedance For a CE stage it is equal to 35 36 Small Signal Model Emitter Degeneration Example I Av g m RC 1 g m RE Av RC 1 RE gm Av Interestingly this gain is equal to the total load resistance to ground divided by 1 gm plus the total resistance placed in series with the emitter 37 Emitter Degeneration Example II Av The input impedance of Q2 can be combined in parallel with RE to yield an equivalent impedance that degenerates Q1 38 Input Impedance of Degenerated CE Stage VA v X r iX RE 1 iX v Rin X r 1 RE iX RC r 2 1 RE g m1 In this example the input impedance of Q2 can be combined in parallel with RC to yield an equivalent collector
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