EECS 105 Spring 2004 Lecture 37 Lecture 37 Frequency response Prof J S Smith Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 37 Prof J S Smith Context We will figure out more of the design parameters for the amplifier we looked at in the last lecture and then we will do a review of the approximate frequency analysis of circuits which have a single dominant pole Department of EECS University of California Berkeley 1 EECS 105 Spring 2004 Lecture 37 Prof J S Smith Reading z Chapter 10 Frequency analysis of active circuits Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 37 Prof J S Smith Lecture Outline z z Department of EECS Finish Example CS NMOS CS PMOS amplifier Review of frequency analysis with a dominant pole University of California Berkeley 2 EECS 105 Spring 2004 Lecture 37 Prof J S Smith Multistage Amplifier Design Example Start with basic two stage transconductance amplifier Why do this combination Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 37 Prof J S Smith Quiescent level shifts NMOS PMOS CS typical typical CG CD known shift known shift Source follower Department of EECS University of California Berkeley 3 EECS 105 Spring 2004 Lecture 37 Prof J S Smith CS CS Amplifier Direct DC connection use NMOS then PMOS Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 37 Prof J S Smith Current Supply Design Assume that the reference is a sink set by a resistor Must mirror the reference current and generate a sink for iSUP 2 Department of EECS University of California Berkeley 4 EECS 105 Spring 2004 Lecture 37 Prof J S Smith Use Basic Current Supplies Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 37 Prof J S Smith Complete Amplifier Topology What s missing The device dimensions the bias voltage and reference resistor Department of EECS University of California Berkeley 5 EECS 105 Spring 2004 Lecture 37 Prof J S Smith DC Bias Find Operating Points Find VBIAS such that VOUT 0 V Device parameters nCox 50 A V2 p Cox 25 A V2 VTn 1 V VTp 1 V n 0 05 V 1 p 0 05 V 1 Device dimensions for lecture design W L n 50 2 W L p 80 2 Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 37 Prof J S Smith Finding RREF V Require IREF ID3 50 A M3 VSG 3 VTp RREF VSG 3 1 V V I REF 50 A 50 A Department of EECS 2I D3 p Cox W L 3 2 50 A 4 1 1 32V 25 A 80 2 40 V VSG 3 V Rref 2 5 1 32 2 5 R Rref ref 74k University of California Berkeley 6 EECS 105 Spring 2004 Lecture 37 Prof J S Smith DC Operating Point IREF 50 A VBIAS VGS 1 Vtn 2 I D1 nCox W L 1 100 A 9 V 50 A V 2 50 2 7 Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 37 Prof J S Smith Small Signal Device Parameters Transistors M1 and M2 ro1 400 k gm1 350 S gm2 315 S ro2 400 k Current supplies iSUP1 and iSUP2 roc1 ro4 400 k roc2 ro6 400 k Department of EECS University of California Berkeley 7 EECS 105 Spring 2004 Lecture 37 Two Port Model Prof J S Smith Find Gm iout vin Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 37 Prof J S Smith Output Voltage Swing Transistors M2 and M6 will limit the output swing Department of EECS University of California Berkeley 8 EECS 105 Spring 2004 Lecture 37 Limits to Output Voltage Prof J S Smith M6 will leave saturation when vOUT drops to vOUT MIN V VDS 6 sat 2 5 2I D6 nCox W L 6 vOUT MIN 2 5 0 28 2 22 V M2 will leave saturation when vOUT rises to vOUT MAX V VSD 2 sat 2 5 2 I D 2 p Cox W L 2 vOUT MAX 2 5 0 32 2 18 V What about M4 Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 37 Prof J S Smith Output Current Swing Load resistor pick RL 25 k Output current iOUT vOUT RL iOUT iD 6 iD 2 iOUT Limits asymmetrical vOUT M2 can increase iD2 M6 can t increase iD6 Department of EECS University of California Berkeley 9 EECS 105 Spring 2004 Lecture 37 Prof J S Smith Output Current Limits Positive output current negative vOUT iOUT MAX iD 6 0 50 A vOUT MIN RL vOUT MIN 50 A 25k 1 25V less negative than limit set by saturation of M6 Negative output current positive vOUT No limit on current from M2 so voltage swing sets current limit iOUT MIN vOUT MAX RL 2 18V 25k 87 2 A Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 37 Prof J S Smith Transfer Curves for RL 25 k Loaded voltage gain vout vin gm1Rout1 gm2Rout RL 490 Loaded transconductance iout vin gm1Rout1 gm2 Rout Rout RL 19 5 mS 2 1 vOUT iOUT A 2 100 1 50 1 0 1 2 Department of EECS 2 vIN 2 1 0 1 50 2 vIN 100 University of California Berkeley 10 EECS 105 Spring 2004 Lecture 37 Prof J S Smith Frequency response The frequency response of single stage transistor CS voltage amplifiers can be modeled with the following small signal model C gd v gs C gs g m vin ro vout We have approximated the frequency response by using the Miller approximation and assuming a single dominant pole Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 37 Prof J S Smith Phasor analysis z As an example problem we will review the Miller Dominant pole approximation for this circuit and phasor analysis and compare the results C gd v gs C gs g m vin ro z vout Using the Miller approximation we replaced Cgs with a capacitance CM to ground where CM 1 g m RL ro C gs Department of EECS A0 University of California Berkeley 11 EECS 105 Spring 2004 Lecture 37 Prof J S Smith Phasor analysis C gd v gs g m vin C gs ro vout Let s take a look at this as a frequency analysis problem Since this is a linear circuit we can drive the circuit at a single frequency and find the voltages at any node and currents through any wire in the circuit in terms of their amplitude and phase Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 37 Prof J S Smith Defining the phasors z We now define the phasors 1 j t I in e C C 2 1 v gs V in e j t C C 2 1 vout V out e j t C C 2 iin Etc Department of EECS University of California Berkeley 12 EECS 105 …
View Full Document
Unlocking...