1Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37Lecture 37: Frequency responseProf J. S. SmithDepartment of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithContextWe will figure out more of the design parameters for the amplifier we looked at in the last lecture, and then we will do a review of the approximate frequency analysis of circuits which have a single dominant pole.2Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithReadingzChapter 10, Frequency analysis of active circuitsDepartment of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithLecture OutlinezFinish Example: CS NMOS->CS PMOS amplifierzReview of frequency analysis (with a dominant pole)3Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithMultistage Amplifier Design ExampleStart with basic two-stage transconductance amplifier:Why do this combination?Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithQuiescent level shiftsPMOSNMOS⇑(known shift)⇓(known shift)CDSource follower⇓⇑CG⇓(typical)⇑(typical)CS4Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithCS→CS AmplifierDirect DC connection: use NMOS then PMOSDepartment of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithCurrent Supply DesignAssume that the reference is a “sink” set by a resistorMust mirror the reference current and generate a sink for iSUP 25Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithUse Basic Current SuppliesDepartment of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithComplete Amplifier TopologyWhat’s missing? The device dimensions,the bias voltage and reference resistor6Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithDC Bias: Find Operating PointsFind VBIASsuch that VOUT= 0 VDevice parameters: =oxnCµ50 µA/V2=oxpCµ25 µA/V2λn= 0.05 V-1λp= 0.05 V-1VTn= 1 V VTp= -1 VDevice dimensions (for “lecture” design): (W/L)n= 50/2 (W/L)p= 80/2Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithFinding RREF V+ V+ V- RREF M3 Require IREF= - ID3= 50 µA333)/(2LWCIVVoxpDTpSGµ−+−=[][]refSGREFRVVVAI−+−−==350µVAAVVSG32.14041)2/80(25502)1(3=+=×−+−−=µµ[][]Ω=⇒−−−= kRRArefref745.232.15.250µ7Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithDC Operating PointIREF=50 µAVVAALWCIVVVoxnDtnGSBIAS79)2/50)(/(501001)/(2211≈+=+==−µµµDepartment of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithSmall-Signal Device Parametersgm1= 350 µSgm2= 315 µSro1= 400 kΩro2= 400 kΩTransistors M1and M2Current supplies iSUP1and iSUP2roc1= ro4=400 kΩroc2= ro6=400 kΩ8Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithTwo-Port ModelFind Gm = iout/ vinDepartment of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithOutput Voltage SwingTransistors M2and M6will limit the output swing9Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithLimits to Output VoltageM6will leave saturation when vOUTdrops to:()66,6,/25.2LWCIVVvoxnDsatDSMINOUTµ+−=+=−M2will leave saturation when vOUTrises to:()22,2,/)(25.2LWCIVVvoxpDsatSDMAXOUTµ−−=−=+What about M4?vOUT,MIN= -2.5 + 0.28 = - 2.22 V vOUT,MAX= 2.5 - 0.32 = 2.18 V Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithOutput Current SwingLoad resistor: pick RL= 25 kΩOutput current:LOUTOUTRvi /−= iOUT vOUT Limits: asymmetricalM2: can increase - iD2M6: can’t increase iD6()26 DDOUTiii−−=10Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithOutput Current Limits• Positive output current (negative vOUT) ()LMINOUTDMAXOUTRvAii /500,6,−==−=µ• Negative output current (positive vOUT) VkAvMINOUT25.1)25)(50(,−=Ω−=µ(less negative than limit set by saturation of M6)No limit on current from M2, so voltage swing setscurrent limitAkVRviLMAXOUTMINOUTµ2.87)25/18.2(/,,−=Ω−=−=Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithTransfer Curves (for RL= 25 kΩ) vOUT vIN 1 2 -1 -20 -1 -2 12 iOUT [µA] vIN 50 100 -50 -100 0 -1 -2 1 2 Loaded voltage gain = vout/vin= (gm1Rout1)(gm2Rout||RL) = 490Loaded transconductance = iout/vin= (-gm1Rout1)(gm2)(Rout/(Rout+ RL) = -19.5 mS11Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithFrequency response• The frequency response of single stage transistor CS voltage amplifiers can be modeled with the following small signal model. • We have approximated the frequency response by using the Miller approximation and assuming a single dominant pole.−+gsv−+outvinmvgorgdCgsCDepartment of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithPhasor analysiszAs an example problem, we will review the Miller/Dominant pole approximation for this circuit, and phasor analysis, and compare the resultszUsing the Miller approximation, we replaced Cgswith a capacitance CMto ground, where:−+gsv−+outvinmvgorgdCgsC()gsoLmMCrRgC )||(1+=0A−12Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithPhasor analysisLet’s take a look at this as a frequency analysis problem. Since this is a linear circuit, we can drive the circuit at a single frequency ω, and find the voltages at any node and currents through any wire in the circuit in terms of their amplitude and phase.−+gsv−+outvinmvgorgdCgsCDepartment of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithDefining the phasorszWe now define the phasors:Etc.()()()..ˆ21..ˆ21..ˆ21CCeVvCCeVvCCeIitjoutouttjingstjinin+=+=+=ωωω13Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 37 Prof. J. S. SmithPhasor analysisThe current into the
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