Lecture 27 ANNOUNCEMENTS Regular office hours will end on Monday 12 10 Special office hours will be posted on the EE105 website Final Exam Review Session Friday 12 14 3PM HP Auditorium Video will be posted online by Monday 12 17 Final Exam Thursday 12 20 12 30PM 3 30PM 277 Cory Closed book 6 pages of notes only Comprehensive in coverage Material of MT 1 and MT 2 plus MOSFET amplifiers MOSFET current sources BJT and MOSFET differential amplifiers feedback Qualitative questions on state of the art device technology EE105 Fall 2007 Lecture 27 Slide 1 Prof Liu UC Berkeley Outline IC technology advancement Q How did we get here Modern BJT technology Q What is an HBT Modern MOSFET technology Q What are the challenges and potential solutions for continued MOSFET scaling EE105 Fall 2007 Lecture 27 Slide 2 Prof Liu UC Berkeley The IC Market The semiconductor industry is approaching 300B yr in sales Military 2 Communications 24 Computers 42 Industrial 8 EE105 Fall 2007 Transportation 8 Lecture 27 Slide 3 Consumer Electronics 16 Courtesy of Dr Bill Flounders UC Berkeley Microlab Prof Liu UC Berkeley IC Technology Advancement Improvements in IC performance and cost have been enabled by the steady miniaturization of the transistor Transistor Scaling SMIC s Fab 4 Beijing China Photo by L R Huang DigiTimes Investment 100 PITCH 2004 2007 2010 2013 2016 HALF PITCH 90nm 65nm 45nm 32nm 22nm EE105 Fall 2007 Lecture 27 Slide 4 GATE LENGTH nm Better Performance Cost Market Growth YEAR International Technology Roadmap for Semiconductors 10 LOW POWER HIGH PERFORMANCE 1 2000 2005 2010 2015 2020 YEAR Prof Liu UC Berkeley The Nanometer Size Scale MOSFET Carbon nanotube EE105 Fall 2007 Lecture 27 Slide 5 Prof Liu UC Berkeley Nanogap DNA Detector Prof Luke Lee BioEngineering Dept http www biopoems berkeley edu Single stranded DNA Double stranded DNA Polysilicon Poly Si Poly Si Poly Si Insulator Si3N4 Insulator Si3N4 EE105 Fall 2007 Poly Si Lecture 27 Slide 6 Prof Liu UC Berkeley IC Fabrication Goal Mass fabrication i e simultaneous fabrication of many IC chips on each wafer each containing millions or billions of transistors Approach Form thin films of semiconductors metals and insulators over an entire wafer and pattern each layer with a process much like printing lithography Planar processing consists of a sequence of additive and subtractive steps with lateral patterning oxidation deposition ion implantation EE105 Fall 2007 etching lithography Lecture 27 Slide 7 Prof Liu UC Berkeley Planar Processing patented by Fairchild Semiconductor in 1959 J A Hoerni US Patent 3 064 167 DEPOSITION of a thin film LITHOGRAPHY Coat with a protective layer Selectively expose the protective layer Develop the protective layer ETCH to selectively remove the thin film Strip etch the protective layer EE105 Fall 2007 Lecture 27 Slide 8 Courtesy of Dr Bill Flounders UC Berkeley Microlab Prof Liu UC Berkeley Overview of IC Process Steps Test Epitaxy Bare Silicon Wafer Processed Wafer Deposition growth Anneal Mask Pattern Generation CMP Ion Implantation CD SEM Metrology Defect Detection Lithography Etch EE105 Fall 2007 Lecture 27 Slide 9 Courtesy of Dr Bill Flounders UC Berkeley Microlab Prof Liu UC Berkeley Modern BJT Structure B E P polySi p C N polySi P polySi p P base N collector Deep trench N Shallow trench subcollector N Deep trench P substrate Features Narrow base n poly Si emitter Self aligned p poly Si base contacts Lightly doped collector Heavily doped epitaxial subcollector Shallow trenches and deep trenches filled with SiO 2 for electrical isolation EE105 Fall 2007 Lecture 27 Slide 10 Prof Liu UC Berkeley BJT Performance Parameters Common emitter current gain IC IB 2 qAE DB niB N BWB 2 qAE DE niE N EWE 2 D n B iB N EWE 2 DE niE N BWB The cutoff frequency fT is the frequency at which falls to 1 It is correlated with the maximum frequency of oscillation fmax Intrinsic gain EE105 Fall 2007 I V V g m ro C A A VT I C VT Lecture 27 Slide 11 Prof Liu UC Berkeley Heterojunction Bipolar Transistor HBT To improve we can increase niB by using a base material Si1 xGex that has a smaller band gap energy for x 0 2 Eg of Si1 xGex is 0 1eV smaller than for Si Eg n exp kT 2 i 2 DB niB N EWE 2 DE niE N BWB Note that this allows a large to be achieved with large NB even NE which is advantageous for increasing Early voltage VA reducing base resistance EE105 Fall 2007 Lecture 27 Slide 12 Prof Liu UC Berkeley Modern MOSFET Structures Intel Penryn from www semiconductor com N channel MOSFETs P channel MOSFETs 45nm CMOS technology features High permittivity gate dielectric and metal gate electrodes strained channel regions shallow trench isolation EE105 Fall 2007 Lecture 27 Slide 13 Prof Liu UC Berkeley MOSFET Performance Parameters Transconductance short channel MOSFET ID g m vWCox VGS VTH The average carrier velocity v is dependent on the velocity at which carriers are injected from the source into the channel which is dependent on the carrier mobility gm The cutoff frequency of a MOSFET is given by 2 f T CGS ID 1 1 g r Intrinsic gain m o V V I V V GS TH D GS TH EE105 Fall 2007 Lecture 27 Slide 14 Prof Liu UC Berkeley MOSFET Scaling Challenges Suppression of short channel effects Gain in ION is incommensurate with Lg scaling Variability in performance Sub wavelength lithography Costly resolution enhancement techniques are needed Random variations Photoresist line edge roughness SiO2 photoresist Statistical dopant fluctuations Source Gate Drain A Asenov Symp VLSI Tech Dig pp 86 87 2007 A Brown et al IEEE Trans Nanotechnology p 195 2002 EE105 Fall 2007 Lecture 27 Slide 15 Prof Liu UC Berkeley VTH Roll Off M Okuno et al 2005 IEDM p 52 VTH decreases with Lg Effect is exacerbated by high values of VDS Qualitative explanation The source drain p n junctions assist in depleting the Si underneath the gate The smaller the Lg the greater the percentage of charge balanced by the S D p n junctions D Large Lg S Small Lg S EE105 Fall 2007 Lecture 27 Slide 16 D Prof Liu UC Berkeley Why New Transistor Structures DIBL must be suppressed to scale down Lg Leakage occurs in region far from channel surface Let s get rid of it Lg Gate Gate Thin Body MOSFET Source Source Drain Drain Buried Oxide Substrate EE105 Fall 2007 Lecture 27 Slide 17 Silicon onInsulator SOI Wafer Prof Liu UC Berkeley Thin Body MOSFETs Leakage is suppressed by using a thin body TSi Lg Channel doping is not needed higher carrier mobility Double gate structure is more scalable to Lg 10nm
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