Lecture 27OutlineThe IC MarketIC Technology AdvancementThe Nanometer Size ScaleNanogap DNA DetectorIC FabricationPlanar Processing (patented by Fairchild Semiconductor in 1959: J. A. Hoerni, US Patent 3,064,167)Overview of IC Process StepsModern BJT StructureBJT Performance ParametersHeterojunction Bipolar Transistor (HBT)Modern MOSFET Structures (Intel Penryn, from www.semiconductor.com)MOSFET Performance ParametersMOSFET Scaling Challenges“VTH Roll-Off”Why New Transistor Structures?Thin-Body MOSFETsDouble-Gate “FinFET”15 nm Lg FinFETs10 nm Lg FinFETsMOSFET Scaling ScenarioThe End is Not the Limit !EECS 105 in the Grand SchemeEE105 Fall 2007 Lecture 27, Slide 1 Prof. Liu, UC BerkeleyLecture 27ANNOUNCEMENTS•Regular office hours will end on Monday 12/10•Special office hours will be posted on the EE105 website•Final Exam Review Session: Friday 12/14, 3PM, HP Auditorium–Video will be posted online by Monday 12/17•Final Exam:–Thursday 12/20, 12:30PM-3:30PM, 277 Cory–Closed book; 6 pages of notes only–Comprehensive in coverage:•Material of MT#1 and MT#2, plus MOSFET amplifiers, MOSFET current sources, BJT and MOSFET differential amplifiers, feedback.•Qualitative questions on state-of-the-art device technologyEE105 Fall 2007 Lecture 27, Slide 2 Prof. Liu, UC BerkeleyOutline•IC technology advancementQ: How did we get here?•Modern BJT technologyQ: What is an HBT?•Modern MOSFET technologyQ: What are the challenges (and potential solutions) for continued MOSFET scaling?EE105 Fall 2007 Lecture 27, Slide 3 Prof. Liu, UC BerkeleyThe IC Market•The semiconductor industry is approaching $300B/yr in salesTransportation 8%Consumer Electronics16%Communications24%Computers42%Industrial8%Military2%Courtesy of Dr. Bill Flounders, UC Berkeley MicrolabEE105 Fall 2007 Lecture 27, Slide 4 Prof. Liu, UC BerkeleyIC Technology AdvancementImprovements in IC performance and cost have been enabled by the steady miniaturization of the transistorBetter Performance/CostMarket Growth2000 2005 2010 2015 2020110100GATE LENGTH (nm)YEAR LOW POWER HIGH PERFORMANCEInternational Technology Roadmap for SemiconductorsTransistor ScalingInvestment SMIC’s Fab 4 (Beijing, China)Photo by L.R. Huang, DigiTimesPITCHYEAR: 2004 2007 2010 2013 2016HALF-PITCH: 90nm 65nm 45nm 32nm 22nmEE105 Fall 2007 Lecture 27, Slide 5 Prof. Liu, UC BerkeleyThe Nanometer Size ScaleCarbon nanotubeMOSFETEE105 Fall 2007 Lecture 27, Slide 6 Prof. Liu, UC BerkeleyNanogap DNA DetectorProf. Luke Lee, BioEngineering Dept.http://www-biopoems.berkeley.edu/Insulator (PolysiliconInsulator (Si3N4)Insulator (Insulator (Si3N4)Poly-SiDouble-stranded DNAPoly-SiSingle-stranded DNAPoly-SiPoly-SiEE105 Fall 2007 Lecture 27, Slide 7 Prof. Liu, UC Berkeley•Goal: Mass fabrication (i.e. simultaneous fabrication) of many IC “chips” on each wafer, each containing millions or billions of transistors•Approach: Form thin films of semiconductors, metals, and insulators over an entire wafer, and pattern each layer with a process much like printing (lithography).IC FabricationPlanar processing consists of a sequence of additive and subtractive steps with lateral patterningoxidationdepositionion implantationetching lithographyEE105 Fall 2007 Lecture 27, Slide 8 Prof. Liu, UC Berkeley•DEPOSITION of a thin film•LITHOGRAPHY–Coat with a protective layer–Selectively expose the protective layer–Develop the protective layer•ETCH to selectively remove the thin film•Strip (etch) the protective layerPlanar Processing(patented by Fairchild Semiconductor in 1959: J. A. Hoerni, US Patent 3,064,167)Courtesy of Dr. Bill Flounders, UC Berkeley MicrolabEE105 Fall 2007 Lecture 27, Slide 9 Prof. Liu, UC BerkeleyDeposition/growthEtchEpitaxyAnnealCMPIon ImplantationTestCD SEMMetrologyDefectDetectionLithographyMask Pattern GenerationBare SiliconWaferProcessedWaferOverview of IC Process StepsCourtesy of Dr. Bill Flounders, UC Berkeley MicrolabEE105 Fall 2007 Lecture 27, Slide 10 Prof. Liu, UC BerkeleyFeatures:• Narrow base • n+ poly-Si emitter• Self-aligned p+ poly-Si base contacts• Lightly-doped collector• Heavily-doped epitaxial subcollector• Shallow trenches and deep trenches filled with SiO2 for electrical isolationB E C p+p+ P base N collectorN+ subcollector PsubstrateN+polySiN+DeeptrenchDeep trench ShallowtrenchP+polySiP+polySiModern BJT StructureEE105 Fall 2007 Lecture 27, Slide 11 Prof. Liu, UC BerkeleyBJT Performance Parameters•Common emitter current gain, :•The cutoff frequency, fT, is the frequency at whichfalls to 1.It is correlated with the maximum frequency of oscillation, fmax.•Intrinsic gainBBiEEEEiBBEEiEEEBBiBBEBCWNnDWNnDWNnDqAWNnDqAII2222TACATComVVIVVIrg EE105 Fall 2007 Lecture 27, Slide 12 Prof. Liu, UC Berkeley•To improve , we can increase niB by using a base material (Si1-xGex) that has a smaller band gap energy• for x = 0.2, Eg of Si1-xGex is 0.1eV smaller than for Si•Note that this allows a large to be achieved with large NB (even >NE), which is advantageous for•increasing Early voltage (VA)•reducing base resistanceHeterojunction Bipolar Transistor (HBT)kTEngiexp2BBiEEEEiBBWNnDWNnD22EE105 Fall 2007 Lecture 27, Slide 13 Prof. Liu, UC BerkeleyModern MOSFET Structures(Intel Penryn, from www.semiconductor.com)•45nm CMOS technology features:– High-permittivity gate dielectric and metal gate electrodes– strained channel regions– shallow trench isolationN-channel MOSFETs P-channel MOSFETsEE105 Fall 2007 Lecture 27, Slide 14 Prof. Liu, UC BerkeleyMOSFET Performance Parameters•Transconductance (short-channel MOSFET):–The average carrier velocity v is dependent on the velocity at which carriers are “injected” from the source into the channel, which is dependent on the carrier mobility•The cutoff frequency of a MOSFET is given by•Intrinsic gain:THGSDoxmVVIvWCg)(11THGSDTHGSDomVVIVVIrgGSmTCgf 2EE105 Fall 2007 Lecture 27, Slide 15 Prof. Liu, UC BerkeleyMOSFET Scaling Challenges•Suppression of short-channel effects–Gain in ION is incommensurate with Lg scaling•Variability in performance–Sub-wavelength lithography:(Costly resolution-enhancement techniques are needed)–Random variations:•Photoresist line-edge roughness•Statistical dopant fluctuationsphotoresist SiO2GateA. Brown et al., IEEE
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