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Berkeley ELENG 105 - Lecture 9 Frequency Response

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EE105 - Spring 2007Microelectronic Devices and CircuitsLecture 9Frequency Response2Chapter 11 Frequency Response 11.1 General Considerations 11.2 High-Frequency Models of Transistors 11.3 Frequency Response of CS Stages 11.4 Frequency Response of CG Stages 11.5 Frequency Response of Followers 11.6 Frequency Response of Cascode Stage 11.7 Frequency Response of Differential Pairs 3High Frequency Roll-off of Amplifier  As frequency of operation increases, the gain of amplifier decreases. This chapter analyzes this problem. 4Gain Roll-off Thru CL The capacitive load, CL, is the culprit for gain roll-off since at high frequency, it will “steal” away some signal current and shunt it to ground.1||m in D outLgVR VCs⎛⎞−=⎜⎟⎝⎠5Frequency Response of the CS Stage At low frequency, the capacitor is effectively open and the gain is flat. As frequency increases, the capacitor tends to a short and the gain starts to decrease. A special frequency is ω=1/(RDCL), where the gain drops by 3dB. 2221out m DinDLVgRVRCω=+6Example: Figure of Merit This metric quantifies a circuit’s gain, bandwidth, and power dissipation. In the bipolar case, low temperature, supply, and load capacitance mark a superior figure of merit.1.. .TCC LFOMVV C=7Bode Plot When we hit a zero, ωzj, the Bode magnitude rises with a slope of +20dB/dec. When we hit a pole, ωpj, the Bode magnitude falls with a slope of -20dB/dec1201211()11zzppssHs Assωωωω⎛⎞⎛⎞++⎜⎟⎜⎟⎝⎠⎝⎠=⎛⎞⎛⎞++⎜⎟⎜⎟⎜⎟⎜⎟⎝⎠⎝⎠LL8Example: Bode Plot The circuit only has one pole (no zero) at 1/(RDCL), so the slope drops from 0 to -20dB/dec as we pass ωp1. 11pDLRCω=9Pole Identification Example I11pSinRCω=21pDLRCω=10Pole Identification Example II111||pSinmRCgω=⎛⎞⎜⎟⎝⎠21pDLRCω=11Circuit with Floating Capacitor The pole of a circuit is computed by finding the effective resistance and capacitance from a node to GROUND.  The circuit above creates a problem since neither terminal of CFis grounded.12Miller’s Theorem  If Avis the gain from node 1 to 2, then a floating impedance ZFcan be converted to two grounded impedances Z1and Z2. 11FvZZA=−211/FvZZA=−13Miller Multiplication With Miller’s theorem, we can separate the floating capacitor. However, the input capacitor is larger than the original floating capacitor. We call this Miller multiplication.14Example: Miller Theorem()11inSmDFRgR Cω=+111outDFmDRCgRω=⎛⎞+⎜⎟⎝⎠15MOS Intrinsic Capacitances For a MOS, there exist oxide capacitance from gate to channel, junction capacitances from source/drain to substrate, and overlap capacitance from gate to source/drain.16Gate Oxide Capacitance Partition and Full Model The gate oxide capacitance is often partitioned between source and drain. In saturation, C2~ Cgate, and C1~ 0. They are in parallel with the overlap capacitance to form CGSand CGD.17Example: Capacitance Identification18Transit Frequency Transit frequency, fT, is defined as the frequency where the current gain from input to output drops to 1.2mTgfCππ=2mTGSgfCπ=19Unified Model for CE and CS Stages20Unified Model Using Miller’s Theorem21Direct Analysis of CE and CS Stages Direct analysis yields different pole locations and an extra zero.() ( )() ( )()12||1||11||mzXYpm L XY Thev Thev in L XY outm L XY Thev Thev in L XY outpThev L in XY out XY in outgCgRCR R C RC CgRCR R C RC CR R CC C C CCωωω==++++++++=++22Example: CE and CS Direct Analysis() ()() ()()( )111 2 1 211 2 1 221211|| ||()1|| ||()||pm O O XY S S in O O XY outm O O XY S S in O O XY outpS O O in XY out XY in outgrr CRRC rr C Cgrr CRRC rr C CRr r CC CC CCωω≈⎡⎤++++⎣⎦⎡⎤++++⎣⎦≈++23Input Impedance of CE and CS Stages()1||1inmCZrCgRCsππμ≈⎡⎤++⎣⎦()11inGS m D GDZCgRC s≈⎡⎤++⎣⎦24Frequency Response of CG Stage Similar to a CB stage, the input pole is on the order of fT, so rarely a speed bottleneck.,,11||1pXSXmXGSSBpYDYYGDDBRCgCCCRCCC Cωω=⎛⎞⎜⎟⎝⎠=+==+Or =∞25Example: CG Stage Pole Identification (),11111||pXSSBGSmRCCgω=⎛⎞+⎜⎟⎝⎠(),112 2211pYDB GD GS DBmCCCCgω=+++26Emitter and Source Followers The following will discuss the frequency response of emitter and source followers using direct analysis. Emitter follower is treated first and source follower is derived easily by allowing rπto go to infinity.27Direct Analysis of Source Follower Stage211GSout minCsVgVasbs+=++()SGD GS GD SB GS SBmGD SBSGDmRaCCCCCCgCCbRCg=+++=+28Example: Source Follower 211GSout minCsVgVasbs+=++[]11 1 1 1 2 2111 2211()( )SGD GS GD GS SB GD DBmGD SB GD DBSGDmRaCCCCCCCgCCCCbRCg=++++++ +=+29Input Capacitance of Emitter/Source Follower1inmLCCCgRπμ=++∞=Or1GSin GDmLCCCgR=++30Example: Source Follower Input Capacitance ()1111 211||in GD GSmO OCC Cgrr=++31Output Impedance of Source Follower1SGSXXGS mRC sVICsg+=+32Active Inductor The plot above shows the output impedance of emitter and source followers. Since a follower’s primary duty is to lower the driving impedance (RS>1/gm), the “active inductor” characteristic on the right is usually observed.33Example: Output Impedance ()12 333|| 1OO GSXXGSmrrCsVICsg+=+∞=Or34Frequency Response of Cascode Stage For cascode stages, there are three poles and Miller multiplication is smaller than in the CE/CS stage.1,21mvXYmgAg−=≈−2xXYCC≈35Poles of MOS Cascode,111211pXmSGS GDmgRC Cgω=⎡⎤⎛⎞++⎢⎥⎜⎟⎝⎠⎣⎦,212 121111pYmDB GS GDmmgCC Cggω=⎡⎤⎛⎞+++⎢⎥⎜⎟⎝⎠⎣⎦(),221p outLDB GDRC Cω=+36MOS Cascode Example,111211pXmSGS GDmgRC Cgω=⎡⎤⎛⎞++⎢⎥⎜⎟⎝⎠⎣⎦,212 13321111pYmDB GS GD GD DBmmgCC CCCggω=⎡⎤⎛⎞+++ ++⎢⎥⎜⎟⎝⎠⎣⎦(),221poutLDB GDRC Cω=+37I/O Impedance of MOS Cascode111211inmGS GDmZgCCsg=⎡⎤⎛⎞++⎢⎥⎜⎟⎝⎠⎣⎦()221||out LGD DBZRCCs=+38MOS Differential Pair Frequency Response Since MOS differential pair can be analyzed using half-circuit, its transfer function, I/O impedances, locations of poles/zeros are the same as that of the half circuit’s.39Example: MOS Differential Pair (),1131,313 131,331[(1/)]1111pXSGS m m GDpYmDB GS GDmmp outLDB GDRC g g CgCC CggRC


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Berkeley ELENG 105 - Lecture 9 Frequency Response

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