Metal Oxide Semiconductor MOS Capacitor EE105 Spring 2007 Microelectronic Devices and Circuits Lecture 4 MOS Capacitors The MOS structure can be thought of as a parallel plate capacitor with the top plate being the positive plate oxide being the dielectric and Si substrate being the negative plate We are assuming P substrate 2 Structure and Symbol of MOSFET MOS Capacitor ox 3 9 0 s 11 7 0 This device is symmetric so either of the n regions can be source or drain MOS Metal Oxide Semiconductor Metal is more commonly a heavily doped n or p polysilicon layer NMOS p type substrate PMOS n type substrate 3 4 Potential Distribution for MOS Capacitor n Gate on p Substrate with Na 1017 cm 3 Charge Distribution at Thermal Equilibrium n 550 mV half of bandgap energy Depletion Width in Substrate Na 10 10 p 60 mV log Steps to construct the potential distribution Gate charges at poly oxide interface Bulk charges in the depletion region of Si substrate Oxide is an insulator No current flowing through oxide 5 Flatband Voltage Gate potential is constant 550 mV for n gate 550 mV for p gate Potential of neutral substrate is constant its value depends on doping Connect the potential between gate and neutral substrate qualitatively Potential varies linearly in oxide Potential varies quadratically in the depletion region of substrate 6 VGB VFB Accumulation Voltage required to produce a flat potential profile Majority carriers holes for psubstrate accumulate at the Si SiO2 interface Occurs when gate bias is below flatband voltage VGB VFB VFB n p Example N a 1017 cm 3 p 60mV 7 420mV n 550mV VFB 970mV Charge distribution Two delta functions QG Cox VGB VFB Cox No net charges at flatband 7 ox tox F cm2 8 VFB VGB VTn Depletion Depletion cont d The majority carriers in Si near oxide interface are depleted Occurs when gate bias between flatband voltage and threshold voltage Charge distribution VGB n p Vox VB qN a xd qN a xd2 Cox 2 s VGB VFB Gate charge at poly SiO2 interface xd tox Fixed acceptor ions in depletion region s ox 2C 2 V VFB 1 ox GB 1 q N a 9 VGB VTn Inversion 10 Inversion Cont d An inversion layer with minority carriers electrons in p substrate is developed at Si SiO2 interface Occurs when gate bias is higher than threshold voltage Charge distributions Electron concentration at SiSiO2 interface q s ns ni e kT N a s p Threshold voltage VTn VFB 2 p Gate charge delta function Inversion layer delta function 1 Cox 2q s N a 2 p After threshold VGB VTn s is pinned at p Inversion charge 0 at threshold Fixed impurity charges constant in depletion region 11 12 Inversion Stops Depletion Q V Curve for MOS Capacitor QG A simple approximation is to assume that once inversion happens the depletion region stops growing on si er v in This is a good assumption since the inversion charge is an exponential function of the surface potential Under this condition dep a QG VTn QB max QG VGB Cox VGB VTn QB max 13 Numerical Example N a 5 10 cm Calculate threshold voltage 3 45 10 13 F cm 2 10 6 cm tox 1 VTn VFB 2 p 2q s N a 2 p Cox VTn 95 2 0 4 VTn VGB V In accumulation the charge is simply proportional to the applied gate body bias In inversion the same is true In depletion the charge grows slower since the voltage is applied over a depletion region 3 VFB n p 550 402 0 95V ox QB max 14 Apply a gate to body voltage 16 Calculate flat band Cox VFB QN VGB Numerical Example Electric Field in Oxide MOS Capacitor with p type substrate tox 20nm um cc n io at ul n letio 2 1 6 10 19 1 04 10 12 5 1016 2 0 4 0 52V Cox 15 VGB 2 5 VFB Device is in accumulation The entire voltage drop is across the oxide Eox Vox VGB n p 2 5 0 55 0 4 V 8 105 6 2 10 cm tox tox The charge in the substrate body consist of holes QB Cox VGB VFB 2 67 10 7 C cm 2 16 MOS CV Curve Numerical Example Depletion Region C In inversion what s the depletion region width and charge QG Cox QN VGB VB max s p p p 2 p 0 8V 1 qN VB max a 2 s X d max qN a QB max 2 X d max 2 sVB max Cox VFB VTn VGB V VFB VGB VTn Small signal capacitance is slope of Q V curve Capacitance is linear in accumulation and inversion Capacitance in depletion region is smallest 144nm QB max qN a X d max 1 15 10 7 C cm 2 Capacitance is non linear in depletion 17 MOS Capacitor n Gate on n Type Substrate C V Curve Equivalent Circuits n 550 mV Cox VFB Cdep Cdep xdep Nd 10 10 n 60 mV log Cox Cox s 18 x Ctot Cdep Cox Cdep Cox tox Cox Cox Cdep s tox 1 1 ox xdep Cox In accumulation mode the capacitance is just due to the voltage drop across tox In inversion the incremental charge comes from the inversion layer depletion region stops growing In depletion region the voltage drop is across the oxide and the depletion region n VTp VTp VFB 2 n 19 1 Cox 2q s N d 2 n 20 MOS Capacitor n Gate on n Type Substrate 21
View Full Document
Unlocking...