EE247 Lecture 13 Administrative issues To avoid having EE247 EE 142 midterms on the same day EE247 midterm moved from Oct 20th to Tues Oct 25th o You can only bring one 8x11 paper with notes o No books class handouts calculators computers cell phones EECS 247 Lecture 13 Data Converters 2005 H K Page 1 EE247 Lecture 13 Data Converters 0Summary last lecture 0ADC DAC testing DNL INL Code boundry servo test Histogram testing Spectral testing Direct Discrete Fourier Transform DFT based measurements DFT measurements including windowing EECS 247 Lecture 13 Data Converters 2005 H K Page 2 Offset and Full Scale Error connect endpoints deriving ideal codes based on non ideal endpoints Real ADC characteristics Ideal converter 7 Digital Output Code For DNL INL measurements need to elliminate offset and full scale error 6 Full scale error 5 4 3 2 1 Offset error 0 1 0 1 2 3 4 5 6 7 8 ADC Input Voltage LSB EECS 247 Lecture 13 Data Converters 2005 H K Page 3 ADC Differential Nonlinearity DNL deviation of code width from 1LSB ADC characteristics ideal converter 8 7 0 4 LSB DNL error Endpoints connected Ideal characterisctics derived DNL measured Digital Output Code 6 5 4 3 0 LSB DNL error 2 1 0 4 LSB DNL error 0 1 0 1 2 3 4 5 6 7 8 9 ADC Input Voltage EECS 247 Lecture 13 Data Converters 2005 H K Page 4 DAC Differential Nonlinearity EECS 247 Lecture 13 Data Converters 2005 H K Page 5 ADC Integral Nonlinearity INL deviation of code transition from its ideal location Ideal converter steps is found for the endpoint line then INL is measured Note that INL errors can be much larger than DNL errors and vice versa EECS 247 Lecture 13 Data Converters Digital Output Code A straight line through the endpoints used as reference offset and full scale errors ignored in INL derivation 7 6 1 LSB INL 5 4 3 2 1 0 1 0 1 2 3 4 5 6 ADC Input Voltage 7 8 2005 H K Page 6 DAC Integral Nonlinearity EECS 247 Lecture 13 Data Converters 2005 H K Page 7 DAC DNL and INL Ref Understanding Data Converters Texas Instruments Application Report SLAA013 Mixed Signal Products 1995 EECS 247 Lecture 13 Data Converters 2005 H K Page 8 Example INL DNL Large INL Small DNL Large DNL Small INL EECS 247 Lecture 13 Data Converters 2005 H K Page 9 Monotonicity Monotonicity guaranteed if INL 0 5 LSB The best fit straight line is taken as the reference for determining the INL This implies DNL 1 LSB Note these conditions are sufficient but not necessary for monotonicity EECS 247 Lecture 13 Data Converters 2005 H K Page 10 How to measure DNL INL DAC Apply codes and use a good voltmeter to measure output ADC Not as simple as DAC need to find decision levels i e input voltages at all code boundaries One way Adjust voltage source to find exact code trip points code boundary servo More versatile Histogram testing Apply a signal with known distibution and analyze digital code distribution at ADC output EECS 247 Lecture 13 Data Converters 2005 H K Page 11 Code Boundary Servo Input Digital Code i1 A C1 VREF fS A B Digital Comp R2 ADC Input A B B ADC Under Test C2 i2 ADC Output EECS 247 Lecture 13 Data Converters 2005 H K Page 12 i1 and i2 are small and C1 is large so the ADC analog input moves a small fraction of an LSB each sampling period For a code input of 101 the ADC analog input settles to the code boundary shown ADC Digital Output Code Boundary Servo 111 110 101 100 011 010 001 000 2 3 4 5 6 7 ADC Analog Input EECS 247 Lecture 13 Data Converters 2005 H K Page 13 Code Boundary Servo Input Digital Code Good DVM i1 A C1 VREF fS A B Digital Comp R2 ADC A B B C2 i2 ADC Output EECS 247 Lecture 13 Data Converters 2005 H K Page 14 Code Boundary Servo A very good digital voltmeter DVM measures the analog input voltage corresponding to the desired code boundary DVMs have some interesting properties They can have very high resolutions 8 decimal digit meters are inexpensive To achieve stable readings DVMs average voltage measurements over multiple 60Hz ac line cycles to filter out pickup in the measurement loop EECS 247 Lecture 13 Data Converters 2005 H K Page 15 Code Boundary Servo ADCs of all kinds are notorious for kicking back high frequency signal dependent glitches to their analog inputs A magnified view of an analog input glitch follows EECS 247 Lecture 13 Data Converters Good DVM VREF fS R2 ADC C2 2005 H K Page 16 Code Boundary Servo analog input Just before the input is sampled and conversion starts the analog input is pretty quiet As the converter begins to quantize the signal it kicks back charge start of conversion 0 1 fS time EECS 247 Lecture 13 Data Converters 2005 H K Page 17 Code Boundary Servo How do we control this error DVM measures the average input including the glitch analog input The difference between what the ADC measures and what the DVM measures is not ADC INL it s error in the INL measurement ADC converts this voltage 0 time EECS 247 Lecture 13 Data Converters 1 fS 2005 H K Page 18 Code Boundary Servo A large C2 fixes this Good DVM At the expense of longer measurement time VREF fS R2 ADC C2 EECS 247 Lecture 13 Data Converters 2005 H K Page 19 Histogram Testing Code boundary measurements are slow Long testing time May miss dynamic errors Histogram testing Quantize input with known pdf e g ramp or sinusoid Measure output pdf Derive INL and DNL from deviation of measured pdf from expected result EECS 247 Lecture 13 Data Converters 2005 H K Page 20 Histogram Test Setup VREF Ramp VREF ADC 0 PC Time Slow wrt conversion time linear ramp applied to ADC DNL derived directly from total number of occurrences of each code the output of the ADC EECS 247 Lecture 13 Data Converters 2005 H K Page 21 A D Histogram Test Using Ramp Signal Digital Output Example ADC Input Output Ramp slope 10 V sec 1LSB 10mV Each ADC code 1msec fs 100kHz Ts 10 sec Analog input n 100 samples code n fs Ramp Time EECS 247 Lecture 13 Data Converters 2005 H K Page 22 Example Ramp slope 10 V usec 1LSB 10mV Each ADC code 1msec Digital Output A D Histogram Test Using Ramp Signal ADC Input Output Analog input fs 100kHz Ts 10 sec n 100 samples code Ramp of Samples Per code Time n fs EECS 247 Lecture 13 Data Converters 2005 H K Page 23 Measuring DNL Ramp speed is adjusted to provide large number of output code e g an average of 100 outputs of each ADC code for 1 100 LSB resolution Ramp test can be quite slow for high resolution ADCs Example 16bit ADC 100conversions …
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