EECS 247 Lecture 21: Data Converters © 2004 H.K. Page 1EE247Lecture 21ADC ConvertersPipelined ADCsEECS 247 Lecture 21: Data Converters © 2004 H.K. Page 2Pipelined A/D Converters• Ideal operation• Errors and correction– Redundancy– Digital calibration• Implementation – Practical circuits– Stage scalingEECS 247 Lecture 21: Data Converters © 2004 H.K. Page 3Block Diagram• Idea: Cascade several low resolution stages to obtain high overall resolution• Each stage performs coarse A/D conversion and computes its quantization error, or "residue"Align and Combine DataStage 1B1 BitsStage 2B2 BitsDigital output(B1 + B2 + ... + Bk) BitsVinMSB... ...LSB Stage k Bk BitsVres1Vres2EECS 247 Lecture 21: Data Converters © 2004 H.K. Page 4Characteristics• Number of components (stages) grows linearly with resolution• Pipelining– Trading latency for conversion speed– Latency may be an issue in e.g. control systems– Throughput limited by speed of one stage → Fast• Versatile: 8...16bits, 1...200MS/s• Many analog circuit non-idealities can be corrected digitallyEECS 247 Lecture 21: Data Converters © 2004 H.K. Page 5Concurrent Stage Operation• Stages operate on the input signal like a shift register• New output data every clock cycle, but each stage introduces ½ clock cycle latencyAlign and Combine DataStage 1B1BitsStage 2B2BitsDigital output(B1+ B2 + ... + Bk) BitsVinStage kBkBitsφ1φ2acquireconvertconvertacquire......CLKφ1φ2EECS 247 Lecture 21: Data Converters © 2004 H.K. Page 6Data Alignment• Digital shift register aligns sub-conversion results in timeStage 2B2BitsVinStage kBkBitsφ1φ2acquireconvertconvertacquire......+ +DoutCLK CLK CLKStage 1B1BitsCLKφ1φ2EECS 247 Lecture 21: Data Converters © 2004 H.K. Page 7Latency[Analog Devices, AD 9226 Data Sheet]EECS 247 Lecture 21: Data Converters © 2004 H.K. Page 8Pipelined ADC Analysis• Ignore timing and use simple static model• Let's first look at "two-stage pipeline"– E.g.: Two cascaded 2-bit ADCs to get 4 bits of total resolutionStage 2B2 BitsVin Stage k Bk Bits+DoutStage 1B1 Bits+Vres1Vres2EECS 247 Lecture 21: Data Converters © 2004 H.K. Page 9Two Stage Example• Using only one ADC: output contains large quantization error• "Missing voltage" or "residue" (-εq1)• Idea: Use second ADC to quantize and add -εq10 1 2 3000110110 1 2 3-1-0.500.51[LSB]ADC Input Voltage [LSB]Vin+Dout= Vin + εq12-bit ADC 2-bit ADC???εq1DoutVinEECS 247 Lecture 21: Data Converters © 2004 H.K. Page 10Two Stage Example• Use DAC to compute missing voltage• Add quantized representation of missing voltage• Why does this help? How about εq2 ? Vin“Coarse“+Dout= Vin+ εq1 2-bit ADC 2-bit ADC“Fine“+-2-bit DAC-εq1-εq1+εq2-εq1+εq2EECS 247 Lecture 21: Data Converters © 2004 H.K. Page 11Two Stage Example• Fine ADC is re-used 22times• Fine ADC's full scale range needs to span only 1 LSB of coarse quantizer221222222⋅==refrefqVVε00 01 10 11Vref1/22−εq100011011First ADC“Coarse“Second ADC“Fine“VinVref1Vref2EECS 247 Lecture 21: Data Converters © 2004 H.K. Page 12Two Stage Pipelined ADC Transfer FunctionDoutVinVref10000000100100011010001010110011110001001101010111100110111101111CoarseBits(MSB)FineBits(LSB)EECS 247 Lecture 21: Data Converters © 2004 H.K. Page 13Two Stage (2+2) Pipelined ADCEECS 247 Lecture 21: Data Converters © 2004 H.K. Page 14Cascading More Stages• LSB of last stage becomes very small • Impractical to generate several VrefVinADC+-DACADCB3 bitsB2 bitsB1 bitsVrefVref /2B1Vref /2(B1+B2)Vref /2(B1+B2+B3)EECS 247 Lecture 21: Data Converters © 2004 H.K. Page 15Gain Elements• Practical pipelines use single Vref• Precision requirements decrease down the pipe– Advantageous for noise, matching (later)VinADCB3 bitsB2 bitsB1 bitsVrefVrefVrefVref 2B1 2B2 2B3+-DACADCEECS 247 Lecture 21: Data Converters © 2004 H.K. Page 16Complete Pipeline StageVin+-B-bitDACB-bitADCDGVresVin00Vrefεq1“ResiduePlot“E.g.:B=2G=22=4VresVrefEECS 247 Lecture 21: Data Converters © 2004 H.K. Page 17Errors• We cannot build perfect ADCs, DACs and gain elements• How can we tolerate/correct errors?• Let's first look at sub-ADC errors• Assumptions:– Ideal DAC, ideal gain elementsEECS 247 Lecture 21: Data Converters © 2004 H.K. Page 18ADC ModelΣΣεq1-G1ΣΣΣεq2-G2ΣΣΣεq(n-1)-Gn-1ΣVin,ADCDout1/Gd11/Gd2Vres1Vres2Vres(n-1)Σ1/Gd(n-1)εqnD1D2D(n-1)Dn∏∏−=−−−=−+−++−+−+=11)1()1(21)1(2212111,1...11njdjqnndnnjdjnqddqdqADCinoutGGGGGGGGGVDεεεεEECS 247 Lecture 21: Data Converters © 2004 H.K. Page 19ADC Model• If the "Analog" and "Digital" gains match exactly, we get:∏−=+=11,njjqnADCinoutGVDεjnjnADCGBB∑−=+=112logEECS 247 Lecture 21: Data Converters © 2004 H.K. Page 20Observations• The aggregate ADC resolution is independent of sub-ADC resolution• Effective stage resolution Bj=log2(Gj)• Conversion error does not (directly) depend on sub-ADC errors!• Only error term in Doutcontains quantization error of last stage• So why do we care about sub-ADC errors?Ø Go back to two stage exampleEECS 247 Lecture 21: Data Converters © 2004 H.K. Page 21Sub-ADC Errors∏−=+=11,njjqnADCinoutGVDε12,GVDqADCinoutε+=Grows outside ½ LSB boundsVin,ADCADCB1bitsVrefVrefVres1Vεq2Vin00VrefVresrefEECS 247 Lecture 21: Data Converters © 2004 H.K. Page 22Sub-ADC ErrorsIdeal 2-Stage Pipelined ADC2-Stage Pipelined ADC with Coarse ADC Comp. OffsetEECS 247 Lecture 21: Data Converters © 2004 H.K. Page 231st-Stage Comparator OffsetFirst stage ADC Levels:(∆ = 1)Ideal comparator threshold: -1, 0, +1Comparator threshold including offset:-1, 0.3, +1ß Problem: Vres1exceeds 2ndpipeline stage overload rangeMissing Code!Overall ADC Transfer CurveVres1Vres2EECS 247 Lecture 21: Data Converters © 2004 H.K. Page 24Three Ways to Deal with Errors...• All involve "sub-ADC redundancy"• Redundancy in stage that produces errors– Choose gain for 2ndstage < 2B1– Higher resolution sub-ADC• Redundancy in succeeding stage(s)EECS 247 Lecture 21: Data Converters © 2004 H.K. Page 25VinVref00VrefVres1Vin,ADCADCB1 bitsVrefVrefεq2Vres1(1) Gain for 2ndstage < 2B1• Choose G1slightly less than 2B1• Effective stage resolution becomes non-integer B1eff=log2G1v Ref: A. Karanicolas et. al., JSSC 12/1993EECS 247 Lecture 21: Data Converters © 2004 H.K.
View Full Document
Unlocking...