EE247 Lecture 21 ADC Converters Pipelined ADCs EECS 247 Lecture 21 Data Converters 2004 H K Page 1 Pipelined A D Converters Ideal operation Errors and correction Redundancy Digital calibration Implementation Practical circuits Stage scaling EECS 247 Lecture 21 Data Converters 2004 H K Page 2 Block Diagram Vin Stage 1 B1 Bits Vres1 Stage 2 B2 Bits Vres2 MSB Stage k Bk Bits LSB Align and Combine Data Digital output B1 B2 Bk Bits Idea Cascade several low resolution stages to obtain high overall resolution Each stage performs coarse A D conversion and computes its quantization error or residue EECS 247 Lecture 21 Data Converters 2004 H K Page 3 Characteristics Number of components stages grows linearly with resolution Pipelining Trading latency for conversion speed Latency may be an issue in e g control systems Throughput limited by speed of one stage Fast Versatile 8 16bits 1 200MS s Many analog circuit non idealities can be corrected digitally EECS 247 Lecture 21 Data Converters 2004 H K Page 4 Concurrent Stage Operation 1 2 Vin CLK acquire convert convert acquire Stage 1 B1 Bits Stage 2 B2 Bits Stage k Bk Bits 1 2 Align and Combine Data Digital output B1 B2 Bk Bits Stages operate on the input signal like a shift register New output data every clock cycle but each stage introduces clock cycle latency EECS 247 Lecture 21 Data Converters 2004 H K Page 5 Data Alignment 1 2 Vin CLK acquire convert convert acquire Stage 1 B1 Bits Stage 2 B2 Bits Stage k Bk Bits 1 2 CLK Dout CLK CLK Digital shift register aligns sub conversion results in time EECS 247 Lecture 21 Data Converters 2004 H K Page 6 Latency Analog Devices AD 9226 Data Sheet EECS 247 Lecture 21 Data Converters 2004 H K Page 7 Pipelined ADC Analysis Ignore timing and use simple static model Vin Stage 1 B1 Bits Vres1 Stage 2 B2 Bits Vres2 Stage k Bk Bits Dout Let s first look at two stage pipeline E g Two cascaded 2 bit ADCs to get 4 bits of total resolution EECS 247 Lecture 21 Data Converters 2004 H K Page 8 Two Stage Example 11 Vin 10 2 bit ADC Dout 2 bit ADC Vin 01 00 0 1 2 3 LSB 1 q1 Dout Vin q1 0 5 0 0 5 1 0 1 2 3 ADC Input Voltage LSB Using only one ADC output contains large quantization error Missing voltage or residue q1 Idea Use second ADC to quantize and add q1 EECS 247 Lecture 21 Data Converters 2004 H K Page 9 Two Stage Example 2 bit ADC Vin 2 bit DAC Coarse q1 2 bit ADC Fine q1 q2 q1 q1 q2 Dout Vin Use DAC to compute missing voltage Add quantized representation of missing voltage Why does this help How about q2 EECS 247 Lecture 21 Data Converters 2004 H K Page 10 Two Stage Example q1 11 V ref1 10 22 Vref1 Vin V ref2 01 Second ADC Fine 00 00 01 10 11 First ADC Coarse Fine ADC is re used 22 times Fine ADC s full scale range needs to span only 1 LSB of coarse quantizer V V q2 ref 2 2 2 ref 1 2 22 2 EECS 247 Lecture 21 Data Converters 2004 H K Page 11 Two Stage Pipelined ADC Transfer Function Dout 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Vref1 Vin Coarse Fine Bits Bits MSB LSB EECS 247 Lecture 21 Data Converters 2004 H K Page 12 Two Stage 2 2 Pipelined ADC EECS 247 Lecture 21 Data Converters 2004 H K Page 13 Cascading More Stages Vref Vref 2B1 Vref 2 B1 B2 Vref 2 B1 B2 B3 Vin B1 bits ADC B2 bits B3 bits DAC ADC LSB of last stage becomes very small Impractical to generate several Vref EECS 247 Lecture 21 Data Converters 2004 H K Page 14 Vref Gain Elements Vref Vref Vref Vin 2B1 B1 bits 2B2 B2 bits ADC DAC ADC 2B3 B3 bits Practical pipelines use single Vref Precision requirements decrease down the pipe Advantageous for noise matching later EECS 247 Lecture 21 Data Converters 2004 H K Page 15 Complete Pipeline Stage Vin Vres G B bit ADC B bit DAC D Vref Residue Plot E g B 2 G 2 2 4 q1 Vres 0 EECS 247 Lecture 21 Data Converters 0 Vin Vref 2004 H K Page 16 Errors We cannot build perfect ADCs DACs and gain elements How can we tolerate correct errors Let s first look at sub ADC errors Assumptions Ideal DAC ideal gain elements EECS 247 Lecture 21 Data Converters 2004 H K Page 17 ADC Model Vin ADC Vres1 G 1 q2 q1 Vres2 G 2 D1 Dout Vres n 1 G n 1 q n 1 D2 1 Gd1 Dn 1 Gd2 1 Gd n 1 G q2 G 1 2 n q2 n 1 Dout Vin ADC q1 1 1 Gd 1 Gd 1 Gd 2 Gdj j 1 EECS 247 Lecture 21 Data Converters qn D n 1 G 1 n 1 qn G n 1 d n 1 Gdj j 1 2004 H K Page 18 ADC Model If the Analog and Digital gains match exactly we get Dout Vin ADC qn n 1 G j j 1 n 1 B ADC Bn log 2G j j 1 EECS 247 Lecture 21 Data Converters 2004 H K Page 19 Observations The aggregate ADC resolution is independent of sub ADC resolution Effective stage resolution Bj log2 Gj Conversion error does not directly depend on sub ADC errors Only error term in Dout contains quantization error of last stage So why do we care about sub ADC errors Go back to two stage example EECS 247 Lecture 21 Data Converters 2004 H K Page 20 Sub ADC Errors Vref Vin ADC Vref Vres1 ADC B1 bits Vref Dout Vin ADC qn n 1 G j 1 Vres Dout Vin ADC 0 0 Vin Vref q2 j q2 G1 Grows outside LSB bounds EECS 247 Lecture 21 Data Converters 2004 H K Page 21 Sub ADC Errors Ideal 2 Stage Pipelined ADC 2 Stage Pipelined ADC with Coarse ADC Comp Offset EECS 247 Lecture 21 Data Converters 2004 H K Page 22 1st Stage Comparator Offset Vres1 Problem Vres1 exceeds 2nd pipeline stage overload range Vres2 Overall ADC Transfer Curve First stage ADC Levels 1 Ideal comparator threshold 1 0 1 Comparator threshold including offset 1 0 3 1 EECS 247 Lecture 21 Data Converters Missing Code 2004 H K Page 23 Three Ways to Deal with Errors All involve sub ADC redundancy Redundancy in stage that produces errors Choose gain for 2nd stage 2B1 Higher resolution sub ADC Redundancy in succeeding stage s EECS 247 Lecture 21 Data Converters 2004 H K Page 24 1 Gain for 2nd stage 2B1 Vref Vin ADC Vref Vres1 ADC B1 bits Vref Vres1 Choose G1 slightly less than 2B1 Effective stage resolution becomes non integer B1eff log2G1 v Ref A Karanicolas et al JSSC 12 1993 0 0 Vin …
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