EECS 247 Lecture 1: Introduction © 2008 H.K. Page 1EECS 247Analog-Digital Interface Integrated Circuits© 2008Instructor: Haideh KhorramabadiUC Berkeley Department of Electrical Engineering and Computer SciencesLecture 1: IntroductionEECS 247 Lecture 1: Introduction © 2008 H.K. Page 2Instructor’s Technical Background• Ph.D., EECS department -UC Berkeley 1985, advisor Prof. P.R. Gray– Thesis topic: Continuous-time CMOS high-frequency filters• Industrial background– 11 years at ATT & Bell Laboratories, N.J., in the R&D area as a circuit designer• Circuits for wireline communications: CODECs, ISDN, and DSL including ADCs (nyquist rate & over-sampled), DACs, filters, VCOs• Circuits intended for wireless applications• Fiber-optics circuits– 3 years at Philips Semiconductors, Sunnyvale, CA • Managed a group in the RF IC department- developed ICs for CDMA & analog cell phones– 3 years @ Broadcom Corp. – Director of Analog/RF ICs in San Jose, CA. • Projects: Gigabit-Ethernet, TV tuners, and DSL circuitry– Currently consultant for IC design • Teaching experience– Has taught/co-taught EE247 @ UCB since 2003– Instructor for short courses offered by MEAD Electronics – Adjunct Prof. @ Rutgers Univ., N.J. : Taught a graduate level IC courseEECS 247 Lecture 1: Introduction © 2008 H.K. Page 3Administrative Issues• Course web page: http://inst.eecs.berkeley.edu/~EE247/fa08 – Course notes will be uploaded on the course website prior to each class – Homeworks & due dates are posted on the course website– Announcements regarding the course will be posted on the home page, please visit course website often• Lectures are web cast http://webcast.berkeley.edu/courses– Please try to attend the classes live to benefit from direct interactions– Make sure you use the provided microphones when asking questions or commenting in the classEECS 247 Lecture 1: Introduction © 2008 H.K. Page 4Office Hours & Grading• Office hours:– Tues./Thurs. 2:30-3:30pm @ 477 Cory Hall (unless otherwise announced in the class) – Extra office hours by appointment– Feel free to discuss issues via email: [email protected]• Course grading: – Homework/project 50%– Midterm 20% (tentative date: Oct. 16)– Final 30%EECS 247 Lecture 1: Introduction © 2008 H.K. Page 5Prerequisites & CAD Tools• Prerequisites– Basic course in signal processing (Laplace and z-transform, discrete Fourier transform) i.e. EE120 – Fundamental circuit concepts i.e. EE105 and EE140 • CAD Tools: – Hspice or Spectre –MatlabEECS 247 Lecture 1: Introduction © 2008 H.K. Page 6Analog-Digital Interface CircuitryDigitalProcessorAnalog/Digital InterfaceAnalog InputAnalog WorldDigital/AnalogInterface0 0 11 1 00 1 01 0 0 11 0 1 00 0 1 0Analog Output• Naturally occurring signals are analog• To process signals in the digital domain∴ Need Analog/Digital & Digital/Analog interface circuitryQuestion: Why not perform the signal processing in the analog domain only & thus eliminate need for A/D & D/A?EECS 247 Lecture 1: Introduction © 2008 H.K. Page 7CMOS Technology Evolution versus Time*Ref: Paul R. Gray UCB EE290 course ‘95International Technology Roadmap for Semiconductors, http://public.itrs.netFor NMOS @ (VGS -Vth = 0.5V )75 80 85 90 95 ’00 ’05 ’10 6u3u2u1.5u1u0.8u0.6u0.35u0.25u0.13u0.1u110100ft [GHz]Year0.18u0.065u0.045uEECS 247 Lecture 1: Introduction © 2008 H.K. Page 8CMOS Device EvolutionProgression from 1975 to 2005• Minimum feature sizes ~X1/100• Cut-off frequency ft~X300• Minimum size device area ~1/L2• Number of interconnect layers ~X8EECS 247 Lecture 1: Introduction © 2008 H.K. Page 9Impact of CMOS Scaling on Digital Signal ProcessingDirect beneficiary of VLSI technology down scaling– Digital circuits deal with “0” & “1” signal levels only Æ Not sensitive to “analog” noise– Si Area/function reduced drastically due to• Shrinking of feature sizes• Multi metal levels for interconnections (currently >8 metal level v.s. only 1 in the 1970s)– Enhanced functionality & flexibility– Amenable to automated design & test– “Arbitrary” precision– Provides inexpensive storage capabilityEECS 247 Lecture 1: Introduction © 2008 H.K. Page 10Analog Signal Processing Characteristics• Sensitive to “analog” noise• Has not fully benefited from technology down scaling:– Supply voltages scale down accordingly Æ Reduced voltage swings Æ more challenging analog design– Reduced voltage swings requires lowering of the circuit noise to keep a constant dynamic rangeÆ Higher power dissipation and chip area• Not amenable to automated design • Extra precision comes at a high price• Rapid progress in DSP has imposed higher demands on analog/digital interface circuitryÆPlenty of room for innovations!EECS 247 Lecture 1: Introduction © 2008 H.K. Page 11Cost/Function ComparisonDSP & Analog• Digital circuitry: Fully benefited from CMOS device scaling– Cost/function decreases by ~29% each yearCost/function X1/30 in 10 years*• Analog circuitry: Not fully benefited from CMOS scaling– Device scaling mandates drop in supply voltagesÆthreaten analog feasibilityCost/function for analog ckt almost constant or increase¾ Rapid shift of function implementation from processing in analog domain to digital & hence increased need for A/D & D/A interface circuitry*Ref: International Technology Roadmap for Semiconductors, http://public.itrs.netEECS 247 Lecture 1: Introduction © 2008 H.K. Page 12Digitally Assisted Analog Circuitry• Analog design has indeed benefited from the availability of inexpensive on-chip digital capabilities• Examples:– Compensating/calibrating ADC & DAC inaccuracies– Automatic frequency tuning of filters & VCOs – DC offset compensationEECS 247
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