EECS 247 Lecture 22: Data Converters © 2006 H.K. Page 1EE247Lecture 22ADC Converters– Comparator design (continued)• Comparator architecture examples– Techniques to reduce flash ADC complexity• Interpolating• FoldingEECS 247 Lecture 22: Data Converters © 2006 H.K. Page 2Summary Last LectureADC Converters –Successive approximation ADCs (continued)–Flash ADC–Flash ADC sources of error• Sparkle code• Meta-stability–Comparator design (to be continued)• Single-stage open-loop amplifier• Cascade of open-loop amplifiers• Problem associated with DC offset– Cascaded output series cancellation– Input series cancellation (today)– Offset cancellation through additional input pair plus offset storage capacitorsEECS 247 Lecture 22: Data Converters © 2006 H.K. Page 3Offset CancellationInput Series CancellationRef: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE Journal of Solid-State Circuits, vol. 13, pp. 499 - 503, August 1978. EECS 247 Lecture 22: Data Converters © 2006 H.K. Page 4Offset CancellationInput Series CancellationRef: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE Journal of Solid-State Circuits, vol. 13, pp. 499 - 503, August 1978. Store offsetNote: Mandates closed-loop stabilityEECS 247 Lecture 22: Data Converters © 2006 H.K. Page 5Offset CancellationInput Series CancellationAmplifyS2, S3 Æ openS1Æ closedExample: A=4 ÆInput-referred offset =Vos/5EECS 247 Lecture 22: Data Converters © 2006 H.K. Page 6Offset CancellationCascaded Input Series Cancellationε2Æcharge injection associated with opening of S4EECS 247 Lecture 22: Data Converters © 2006 H.K. Page 7Offset CancellationInput Series Cancellation• Advantages:– In applications such as C-array successive approximation ADCs can use C-array to store offset• Disadvantages:– Cancellation not complete– Requires closed loop stability– Offset storage C in the signal path- could slow down overall performanceEECS 247 Lecture 22: Data Converters © 2006 H.K. Page 8CMOS ComparatorsCascade of Gain StagesFully differential gain stages Æ 1storder cancellation of switch feedthrough offset1-Output series offset cancellation2- Input series offset cancellationEECS 247 Lecture 22: Data Converters © 2006 H.K. Page 9CMOS ComparatorsCascade of Gain Stages3-Combined input & output series offset cancellationEECS 247 Lecture 22: Data Converters © 2006 H.K. Page 10Offset Cancellation• Cancel offset by additional pair of inputs (Lecture 20 slide 16 -18)EECS 247 Lecture 22: Data Converters © 2006 H.K. Page 11Latched ComparatorsVi+Vi--Vout (Digital Output)+-LatchVoutVi+ - Vi-tLatchtt“1”“0”Compares two input voltages at time tx& generates a digital output:If Vi+-Vi-> 0 Æ Vout=“1”If Vi+-Vi-< 0 Æ Vout=“0”txEECS 247 Lecture 22: Data Converters © 2006 H.K. Page 12CMOS Latched ComparatorsComparator amplification need not be linearÆ can use a latch Æ regenerationLatchÆ Amplification + positive feedbackEECS 247 Lecture 22: Data Converters © 2006 H.K. Page 13Simplest Form of CMOS LatchVDDM1M2M3VDDM1M2M4EECS 247 Lecture 22: Data Converters © 2006 H.K. Page 14CMOS Latched ComparatorsSmall Signal ModelLatch can be modeled as a:Æ Single-pole amp + positive feedbackSmall signal ac half circuitEECS 247 Lecture 22: Data Converters © 2006 H.K. Page 15CMOS Latched ComparatorLatch Delay22112D2111111111Integrating both sides: 1 ln ln ln lnLatch Delay:1ln11mLmmmL mLtV aambtV bmLmmLVdVgV CRdtgdVg dVVdtCgR dt CgR Vgadt dV dx x a bCgR V x bCVtttgVgR=+⎛⎞ ⎛⎞−= − =⎜⎟ ⎜⎟⎝⎠ ⎝⎠⎛⎞ ⎛ ⎞−= ==−=⎜⎟⎜⎟⎝⎠⎝⎠⎛⎞⎛⎞=−=⎜⎟⎜⎝−⎜⎟⎜⎟⎝⎠∫∫ ∫2D1For 1lnmLmgRCVtgV⎟⎠>>⎛⎞≈⎜⎟⎝⎠EECS 247 Lecture 22: Data Converters © 2006 H.K. Page 16CMOS Latched Comparators2D121DlnlnmLLmCVtgVVLatchGain AVCtAg⎛⎞≈⎜⎟⎝⎠→=→≈Compared to a 3-stage open-loop cascade of amps for equal overall gain of 1000ÆLatch faster by about x3Normalized Latch DelayDmtCgτD(3-state amp)= 18.2(C/gm)EECS 247 Lecture 22: Data Converters © 2006 H.K. Page 17Latch-Only Comparator• Much faster compared to cascade of open-loop amplifiers• Main problem associated with latch-only comparator topology:– High input-referred offset voltage (as high as 100mV!)• Solution:– Use preamplifier to amplify the signal and reduce overall input-referred offsetEECS 247 Lecture 22: Data Converters © 2006 H.K. Page 18Pre-Amplifier + LatchOverall Input-Referred OffsetLatchVi+Vi-Do+Do-fsPreampAvVosLatchVosPreamp22Re _ _ Pr _2Pr_Pr _ Pr22Re _21: 4 & 50 & 1014506.410Input ferred Offset Vos eamp Vos LatcheampVos eamp Vos Latch eampInput ferred OffsetAExample mV mV AmVσσσσσσ−−=+====+ =Latch offset attenuated by preamp gain when referred to preamp input.Assuming the two offset sources are uncorrelated:EECS 247 Lecture 22: Data Converters © 2006 H.K. Page 19Pre-Amplifier Tradeoffs•Example:– Latch offset 50 to 100mV– Preamp DC gain 10X– Preamp input-referred latch offset 5 to 10mV– Input-referred preamplifier offset 2 to 10mV– Overall input-referred offset 5.5 to 14mVÆ Addition of preamp reduces the latch input-referred offset reduced by ~7 to 9X Æ ~extra 3-bit resolution!LatchVi+Vi-Do+Do-fsPreampAvEECS 247 Lecture 22: Data Converters © 2006 H.K. Page 20Comparator Preamplifier Gain-Speed Tradeoffs• Amplifier maximum Gain-Bandwidth product (fu)for a given technology, typically a function of maximum device ftÆ Tradeoff:• To reduce the effect of latch offset Æ high preamp gain desirable• Fast comparator Æ low preamp gain 0 0 0 preamp 0 preamp 0 0 =unity gain frequency, 3 frequency & settling timeFor example assuming preamp has a gain of 10:11001011.6 sec2uuuffdBffAf GHzfMHzAnfττπ=− ========fu=0.1-10GHzf0fuFrequencyMagnitudeAvEECS 247 Lecture 22: Data Converters © 2006 H.K. Page 21Latched ComparatorAvLatchVi+Vi-Do+Do-fsPreampImportant features:– Maximum clock rate fs Æ settling time, slew rate, small signal bandwidth– ResolutionÆ gain, offset– Overdrive recovery– Input capacitance (and linearity of input capacitance!)– Power dissipation– Input common-mode range and CMR – Kickback noise–…EECS 247 Lecture 22: Data Converters © 2006 H.K. Page 22Comparators Overdrive RecoveryUÆ amplification after time taDuring reset amplifier settles exponentially to
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