EE247 Lecture 22 ADC Converters Comparator design continued Comparator architecture examples Techniques to reduce flash ADC complexity Interpolating Folding EECS 247 Lecture 22 Data Converters 2006 H K Page 1 Summary Last Lecture ADC Converters Successive approximation ADCs continued Flash ADC Flash ADC sources of error Sparkle code Meta stability Comparator design to be continued Single stage open loop amplifier Cascade of open loop amplifiers Problem associated with DC offset Cascaded output series cancellation Input series cancellation today Offset cancellation through additional input pair plus offset storage capacitors EECS 247 Lecture 22 Data Converters 2006 H K Page 2 Offset Cancellation Input Series Cancellation Ref R Poujois and J Borel A low drift fully integrated MOSFET operational amplifier IEEE Journal of Solid State Circuits vol 13 pp 499 503 August 1978 EECS 247 Lecture 22 Data Converters 2006 H K Page 3 Offset Cancellation Input Series Cancellation Store offset Note Mandates closed loop stability Ref R Poujois and J Borel A low drift fully integrated MOSFET operational amplifier IEEE Journal of Solid State Circuits vol 13 pp 499 503 August 1978 EECS 247 Lecture 22 Data Converters 2006 H K Page 4 Offset Cancellation Input Series Cancellation Amplify S2 S3 open S1 closed Example A 4 Input referred offset Vos 5 EECS 247 Lecture 22 Data Converters 2006 H K Page 5 Offset Cancellation Cascaded Input Series Cancellation 2 charge injection associated with opening of S4 EECS 247 Lecture 22 Data Converters 2006 H K Page 6 Offset Cancellation Input Series Cancellation Advantages In applications such as C array successive approximation ADCs can use C array to store offset Disadvantages Cancellation not complete Requires closed loop stability Offset storage C in the signal path could slow down overall performance EECS 247 Lecture 22 Data Converters 2006 H K Page 7 CMOS Comparators Cascade of Gain Stages Fully differential gain stages 1st order cancellation of switch feedthrough offset 1 Output series offset cancellation 2 Input series offset cancellation EECS 247 Lecture 22 Data Converters 2006 H K Page 8 CMOS Comparators Cascade of Gain Stages 3 Combined input output series offset cancellation EECS 247 Lecture 22 Data Converters 2006 H K Page 9 Offset Cancellation Cancel offset by additional pair of inputs Lecture 20 slide 16 18 EECS 247 Lecture 22 Data Converters 2006 H K Page 10 Latched Comparators Vi Vi Vi ViVout Digital Output t Latch Compares two input voltages at time tx generates a digital output If Vi Vi 0 Vout 1 If Vi Vi 0 Vout 0 Latch Vout t tx 1 0 EECS 247 Lecture 22 Data Converters t 2006 H K Page 11 CMOS Latched Comparators Comparator amplification need not be linear can use a latch regeneration Latch Amplification positive feedback EECS 247 Lecture 22 Data Converters 2006 H K Page 12 Simplest Form of CMOS Latch VDD VDD M3 M4 M1 M2 EECS 247 Lecture 22 Data Converters M1 M2 2006 H K Page 13 CMOS Latched Comparators Small Signal Model Latch can be modeled as a Single pole amp positive feedback Small signal ac half circuit EECS 247 Lecture 22 Data Converters 2006 H K Page 14 CMOS Latched Comparator Latch Delay g mV V dV C RL dt gm dV 1 V 1 C g m RL dt gm dV 1 dt 1 C g m RL V Integrating both sides V2 1 gm 1 t2 dt dV 1 1 1 V t V C g m RL a a a1 b dx ln x b ln a ln b ln b x Latch Delay C 1 gm 1 1 g m RL For g m RL 1 tD t2 t1 tD V2 ln V 1 C V2 ln g m V1 EECS 247 Lecture 22 Data Converters 2006 H K Page 15 CMOS Latched Comparators Normalized Latch Delay tD C V2 ln g m V1 V2 Latch Gain AL V1 tD tD C gm D 3 state amp C ln AL gm EECS 247 Lecture 22 Data Converters 18 2 C gm Compared to a 3 stage open loop cascade of amps for equal overall gain of 1000 Latch faster by about x3 2006 H K Page 16 Latch Only Comparator Much faster compared to cascade of openloop amplifiers Main problem associated with latch only comparator topology High input referred offset voltage as high as 100mV Solution Use preamplifier to amplify the signal and reduce overall input referred offset EECS 247 Lecture 22 Data Converters 2006 H K Page 17 Pre Amplifier Latch Overall Input Referred Offset VosLatch VosPreamp fs Vi Vi Latch Av Do Do Preamp Latch offset attenuated by preamp gain when referred to preamp input Assuming the two offset sources are uncorrelated 2 Input Re ferred Offset Vos Pr eamp 1 2 Vos Latch 2 APr eamp Example Vos Pr eamp 4mV Vos Latch 50mV Input Re ferred Offset 42 EECS 247 Lecture 22 Data Converters 1 102 APr eamp 10 502 6 4mV 2006 H K Page 18 Pre Amplifier Tradeoffs fs Vi Vi Example Av Do Latch Do Preamp Latch offset Preamp DC gain Preamp input referred latch offset Input referred preamplifier offset Overall input referred offset 50 to 100mV 10X 5 to 10mV 2 to 10mV 5 5 to 14mV Addition of preamp reduces the latch input referred offset reduced by 7 to 9X extra 3 bit resolution EECS 247 Lecture 22 Data Converters 2006 H K Page 19 Comparator Preamplifier Gain Speed Tradeoffs Amplifier maximum Gain Bandwidth product fu for a given technology typically a function of maximum device ft fu unity gain frequency f 0 3dB frequency 0 settling time f0 fu Apreamp For example assuming preamp has a gain of 10 fu 1GHz 100 MHz f0 Apreamp 10 0 1 1 6n sec 2 f 0 Magnitude Av fu 0 1 10GHz f0 fu Frequency Tradeoff To reduce the effect of latch offset high preamp gain desirable Fast comparator low preamp gain EECS 247 Lecture 22 Data Converters 2006 H K Page 20 Latched Comparator fs Vi Vi Av Do Latch Do Preamp Important features Maximum clock rate fs settling time slew rate small signal bandwidth Resolution gain offset Overdrive recovery Input capacitance and linearity of input capacitance Power dissipation Input common mode range and CMR Kickback noise EECS 247 Lecture 22 Data Converters 2006 H K Page 21 Comparators Overdrive Recovery Linear model for a single pole amplifier U amplification after time ta During reset amplifier settles exponentially to its zero input condition with 0 RC Example Worst case input output waveforms Assume Vm maximum input normalized to 1 2lsb 1 Previous input max possible e g VFS Current input min input referred signal 0 5LSB EECS 247 Lecture 22 Data Converters 2006 H K Page 22 Comparators Overdrive Recovery Example Worst case input output waveforms If recovery time is not long enough to allow output to discharge recover from previous state then it may not be able to resolve the current input error To minimize this effect 1 Passive clamp 2 Active restore 3 Low gain stage
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