EECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 1EE247Lecture 16• D/A Converters (continued)– DAC reconstruction filter• ADC Converters– Sampling• Sampling switch considerations– Thermal noise due to switch resistance – Clock jitter related non-idealities– Sampling switch bandwidth limitations– Switch conductance non-linearity induced distortion• Sampling switch conductance dependence on input voltage• Clock voltage boosters– Sampling switch charge injection & clock feedthroughEECS 247 Lecture 16: Data Converters- DAC Design © 2010 Page 2Summary Last Lecture• D/A converters– Practical aspects of current-switched DACs (continued)– Segmented current-switched DACs– DAC dynamic non-idealities– DAC design considerations– Self calibration techniques• Current copiers• Dynamic element matchingEECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 3DAC In the Big Picture• Learned to build DACs– Convert the incoming digital signal to analog• DAC output staircase form• Some applications require filtering (smoothing) of DAC output Reconstruction filterAnalog Post processingD/AConversionDSPA/D ConversionAnalog PreprocessingAnalog InputAnalog Output000...001...110Anti-AliasingFilterSampling+Quantization"Bits to Staircase"Reconstruction FilterEECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 4DAC Reconstruction Filter• Need for and requirements depend on application• Tasks:– Correct for sinc droop– Remove “aliases”(stair-case approximation)B fs/20 0.5 1 1.5 2 2.5 3x 10600.51DAC Input0 0.5 1 1.5 2 2.5 3x 10600.51sinc0 0.5 1 1.5 2 2.5 300.51DAC OutputNormalized Frequencyf/fsEECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 5Reconstruction Filter Options• Reconstruction filter options:– Continuous-time filter only– CT + SC filter• SC filter possible only in combination with oversampling (signal bandwidth B << fs/2)• Digital filter– Band limits the input signal prevent aliasing– Could also provide high-frequency pre-emphasis to compensate in-band sinx/x amplitude droop associated with the inherent DAC S/H functionDigitalFilterDACSCFilterCTFilterReconstruction FiltersEECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 6DAC Reconstruction Filter Example: Voice-Band CODEC Receive PathRef: D. Senderowicz et. al, “A Family of Differential NMOS Analog Circuits for PCM Codec Filter Chip,” IEEE Journal of Solid-State Circuits, Vol.-SC-17, No. 6, pp.1014-1023, Dec. 1982.Note: fsigmax = 3.4kHzfsDAC = 8kHzsin(p fsigmax x Ts )/(p fsigmax xTs )= -2.75 dB droop due to DAC sinx/x shapeReceive Outputfs= 8kHzfs= 128kHzfs= 8kHzfs= 128kHzfs= 128kHzGSRReconstruction Filter& sinx/x CompensatorEECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 7SummaryD/A Converter • D/A architecture – Unit element – complexity proportional to 2B- excellent DNL – Binary weighted- complexity proportional to B- poor DNL– Segmented- unit element MSB(B1)+ binary weighted LSB(B2) Complexity proportional ((2B1-1) + B2) -DNL compromise between the two• Static performance– Component matching• Dynamic performance– Time constants, Glitches• DAC improvement techniques – Symmetrical switching rather than sequential switching– Current source self calibration– Dynamic element matching• Depending on the application, reconstruction filter may be neededEECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 8What Next?• ADC Converters:– Need to build circuits that "sample“– Need to build circuits for amplitude quantizationAnalog Post processingD/AConversionDSPA/D ConversionAnalog PreprocessingAnalog InputAnalog Output000...001...110Anti-AliasingFilterSampling+Quantization"Bits to Staircase"Reconstruction FilterEECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 9Analog-to-Digital Converters•Two categories:– Nyquist rate ADCs fsigmax~ 0.5xfsampling• Maximum achievable signal bandwidth higher compared to oversampled type• Resolution limited to <14bits– Oversampled ADCs fsigmax<< 0.5xfsampling• Maximum achievable signal bandwidth significantly lower compared to nyquist• Maximum achievable resolution high (18 to 20bits!)EECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 10MOS Sampling CircuitsEECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 11Ideal Sampling• In an ideal world, zero resistance sampling switches would close for the briefest instant to sample a continuous voltage vINonto the capacitor COutput Dirac-like pulses with amplitude equal to VINat the time of sampling• In practice not realizable!vINvOUTCS111T=1/fSEECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 12Ideal Track & Hold SamplingvINvOUTCS11• Vouttracks input for ½ clock cycle when switch is closed• Ideally acquires exact value of Vinat the instant the switch opens• "Track and Hold" (T/H) (often called Sample & Hold!)1T=1/fSEECS 247 Lecture 15: Data Converters- DAC Design & Intro. to ADCs © 2010 Page 13Ideal T/H SamplingContinuousTimeT/H signal(Sampled-DataSignal)ClockDiscrete-TimeSignaltimeTrackHoldEECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 14Practical SamplingIssuesvINvOUTCM11• Switch induced noise due to M1 finite channel resistance• Clock jitter (edge variation of 1)• Finite Rsw limited bandwidth finite acquisition time• Rsw= f(Vin) distortion• Switch charge injection & clock feedthroughEECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 15Sampling Circuit kT/C Noise• Switch resistance & sampling capacitor form a low-pass filter • Noise associated with the switch resistance results in Total noise variance= kT/C @ the output (see noise analysis in Lecture 1)• In high resolution ADCs with such sampling circuit right at the input, kT/C noise at times dominates overall minimum signal handling capability (power dissipation considerations).vINvOUTCS1RvINvOUTCM114kTRDfEECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 16Sampling Network kT/C NoiseFor ADCs sampling capacitor size is usually chosen
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