EE247 Lecture 16 D A Converters continued DAC reconstruction filter ADC Converters Sampling Sampling switch considerations Thermal noise due to switch resistance Clock jitter related non idealities Sampling switch bandwidth limitations Switch conductance non linearity induced distortion Sampling switch conductance dependence on input voltage Clock voltage boosters Sampling switch charge injection clock feedthrough EECS 247 Lecture 16 Data Converters ADC Design 2010 Page 1 Summary Last Lecture D A converters Practical aspects of current switched DACs continued Segmented current switched DACs DAC dynamic non idealities DAC design considerations Self calibration techniques Current copiers Dynamic element matching EECS 247 Lecture 16 Data Converters DAC Design 2010 Page 2 DAC In the Big Picture Analog Input Learned to build DACs Analog Preprocessing Convert the incoming digital signal to analog 000 001 110 DSP Some applications require filtering smoothing of DAC output Reconstruction filter EECS 247 Lecture 16 Sampling Quantization A D Conversion DAC output staircase form Anti Aliasing Filter D A Conversion Bits to Staircase Analog Post processing Reconstruction Filter Analog Output Data Converters ADC Design 2010 Page 3 DAC Reconstruction Filter Need for and requirements depend on application DAC Input B fs 2 1 0 5 0 0 0 5 1 1 5 2 2 5 sinc Tasks x 10 0 5 0 DAC Output Correct for sinc droop Remove aliases stair case approximation 0 0 5 1 1 5 2 2 5 3 6 1 x 10 0 5 0 0 0 5 1 1 5 2 2 5 Normalized Frequency EECS 247 Lecture 16 3 6 1 Data Converters ADC Design 3 f fs 2010 Page 4 Reconstruction Filter Options Reconstruction Filters Digital Filter DAC SC Filter CT Filter Reconstruction filter options Continuous time filter only CT SC filter SC filter possible only in combination with oversampling signal bandwidth B fs 2 Digital filter Band limits the input signal prevent aliasing Could also provide high frequency pre emphasis to compensate inband sinx x amplitude droop associated with the inherent DAC S H function EECS 247 Lecture 16 Data Converters ADC Design 2010 Page 5 DAC Reconstruction Filter Example Voice Band CODEC Receive Path Receive Output fs 8kHz fs 8kHz fs 128kHz fs 128kHz Reconstruction Filter sinx x Compensator GSR fs 128kHz Note fsigmax 3 4kHz fsDAC 8kHz sin p fsigmax x Ts p fsigmax xTs 2 75 dB droop due to DAC sinx x shape Ref D Senderowicz et al A Family of Differential NMOS Analog Circuits for PCM Codec Filter Chip IEEE Journal of Solid State Circuits Vol SC 17 No 6 pp 1014 1023 Dec 1982 EECS 247 Lecture 16 Data Converters ADC Design 2010 Page 6 Summary D A Converter D A architecture Unit element complexity proportional to 2B excellent DNL Binary weighted complexity proportional to B poor DNL Segmented unit element MSB B1 binary weighted LSB B2 Complexity proportional 2B1 1 B2 DNL compromise between the two Static performance Component matching Dynamic performance Time constants Glitches DAC improvement techniques Symmetrical switching rather than sequential switching Current source self calibration Dynamic element matching Depending on the application reconstruction filter may be needed EECS 247 Lecture 16 Data Converters ADC Design 2010 Page 7 What Next Analog Input ADC Converters Analog Preprocessing Anti Aliasing Filter Sampling Quantization Need to build circuits that sample A D Conversion Need to build circuits for amplitude quantization D A Conversion Bits to Staircase Analog Post processing Reconstruction Filter DSP 000 001 110 Analog Output EECS 247 Lecture 16 Data Converters ADC Design 2010 Page 8 Analog to Digital Converters Two categories Nyquist rate ADCs fsigmax 0 5xfsampling Maximum achievable signal bandwidth higher compared to oversampled type Resolution limited to 14bits Oversampled ADCs fsigmax 0 5xfsampling Maximum achievable signal bandwidth significantly lower compared to nyquist Maximum achievable resolution high 18 to 20bits EECS 247 Lecture 16 Data Converters ADC Design 2010 Page 9 MOS Sampling Circuits EECS 247 Lecture 16 Data Converters ADC Design 2010 Page 10 Ideal Sampling In an ideal world zero resistance sampling switches would close for the briefest instant to sample a continuous voltage v IN onto the capacitor C Output Dirac like pulses with amplitude equal to VIN at the time of sampling 1 vIN vOUT S1 C 1 T 1 fS In practice not realizable EECS 247 Lecture 16 Data Converters ADC Design 2010 Page 11 Ideal Track Hold Sampling 1 vIN vOUT S1 1 T 1 fS C Vout tracks input for clock cycle when switch is closed Ideally acquires exact value of Vin at the instant the switch opens Track and Hold T H often called Sample Hold EECS 247 Lecture 16 Data Converters ADC Design 2010 Page 12 Ideal T H Sampling time Hold T H signal Sampled Data Signal Track Continuous Time Clock Discrete Time Signal EECS 247 Lecture 15 Data Converters DAC Design Intro to ADCs 2010 Page 13 Practical Sampling Issues 1 vIN vOUT M1 C Switch induced noise due to M1 finite channel resistance Clock jitter edge variation of 1 Finite Rsw limited bandwidth finite acquisition time Rsw f Vin distortion Switch charge injection clock feedthrough EECS 247 Lecture 16 Data Converters ADC Design 2010 Page 14 Sampling Circuit kT C Noise 1 vIN 4kTRDf vOUT M1 vIN R vOUT S1 C C Switch resistance sampling capacitor form a low pass filter Noise associated with the switch resistance results in Total noise variance kT C the output see noise analysis in Lecture 1 In high resolution ADCs with such sampling circuit right at the input kT C noise at times dominates overall minimum signal handling capability power dissipation considerations EECS 247 Lecture 16 Data Converters ADC Design 2010 Page 15 Sampling Network kT C Noise For ADCs sampling capacitor size is usually chosen based on having thermal noise smaller or equal or at times slightly larger compared to quantization noise Assumption Nyquist rate ADC D2 For a Nyquist rate ADC Total quantizati on noise power 12 Choose C such that thermal noise level is less or equal than Q noise k BT D2 C 12 2B 1 C 12k BT V FS C 12k BT EECS 247 Lecture 16 2 22 B VFS 2 Data Converters ADC Design 2010 Page 16 Sampling Network kT C Noise C 12k BT 22 B VFS 2 Required Cmin as a Function of ADC Resolution B Cmin VFS 1V Cmin VFS 0 5V 8 12 14 16 20 0 003 pF 0 8 pF 13 pF 206 pF 52 800 pF 0 012 pF 2 4 pF 52 pF 824 pF 211 200 pF The large area required for C limit highest achievable resolution for Nyquist rate ADCs Oversampling results in reduction of required value for C will be
View Full Document
Unlocking...