EE247 Lecture 15 Administrative issues Midterm exam postponed to Thurs Oct 25th o You can only bring one 8x11 paper with your own written notes please do not photocopy o No books class or any other kind of handouts notes calculators computers PDA cell phones o Midterm includes material covered to end of lecture 14 o Also reading material including IEEE publications for Nyquist rate data converters posted EECS 247 Lecture 15 Data Converters DAC Design continued 2007 H K Page 1 EE247 Lecture 15 D A converters continued R 2R type DACs Static performance of D As Component matching Systematic random errors Practical aspects of current switched DACs Segmented current switched DACs DAC self calibration techniques Current copiers Dynamic element matching EECS 247 Lecture 15 Data Converters DAC Design continued 2007 H K Page 2 Summary Last Lecture Data Converters Data converter testing continued DNL SNR INL SFDR Effective number of bits ENOB D A converter architectures Resistor string DAC Serial charge redistribution DAC Parallel charge scaling DAC Combination of resistor string MSB binary weighted charge scaling LSB Current source DAC Unit element Binary weighted EECS 247 Lecture 15 Data Converters DAC Design continued 2007 H K Page 3 R 2R Ladder Type DAC R 2R DAC basics R Simple R network divides both voltage current by 2 V V 2 I 2 I 2 I 2R 2R Increase of bits by replicating circuit EECS 247 Lecture 15 Data Converters DAC Design continued 2007 H K Page 4 R 2R Ladder DAC Iout VB R R VEE 2R 2R 2R R 2R 2R 2R R Emitter follower added to convert to high output impedance current sources EECS 247 Lecture 15 Data Converters DAC Design continued 2007 H K Page 5 R 2R Ladder DAC How Does it Work Consider a simple 3bit R 2R DAC Iout VB VEE EECS 247 Lecture 15 4xAunit 2R R 2xAunit 1xAunit 1xAunit 2R 2R 2R R Data Converters DAC Design continued 2007 H K Page 6 R 2R Ladder DAC How Does it Work Simple 3bit DAC 1 Consolidate first two stages I2 I3 VB VEE IT I1 VB Q3 Q2 Aunit 4Aunit 2Aunit 2Aunit 2R 2R R 2R R R Q3 Q2 Q1 QT 4Aunit 2Aunit Aunit 2R R 2R R 2R VEE EECS 247 Lecture 15 I1 IT I2 I3 Data Converters DAC Design continued 2007 H K Page 7 R 2R Ladder DAC How Does it Work Simple 3bit DAC2 Consolidate next two stages I2 I3 VB VEE I1 IT Q3 Q2 4Aunit 2Aunit 2R R 2R R I2 I1 IT I3 VB Q3 Q2 2Aunit 4Aunit 4Aunit R 2R R R VEE I I I I3 I2 I1 IT I3 T ot al I2 T ot a l I1 To t al 2 4 8 EECS 247 Lecture 15 Data Converters DAC Design continued 2007 H K Page 8 R 2R Ladder DAC How Does it Work Consider a simple 3bit R 2R DAC Iout VB 4Aunit 4I VEE Aunit 2Aunit 2R 2I R 4I 2R I I 2R Aunit 2R R 2I In most cases need to convert output current to voltage Ref B Razavi Data Conversion System Design IEEE Press 1995 page 84 87 EECS 247 Lecture 15 Data Converters DAC Design continued 2007 H K Page 9 R 2R Ladder DAC RTotal R Vout VB 16I VEE 2R 8I R 2R 4I R 2R 2I R 16I 8I 4I I 2R 2R I 2R R 2I Trans resistance amplifier added to Convert current to voltage Generate virtual ground current summing node so that output impedance of current sources do not cause error Issue error due to opamp offset EECS 247 Lecture 15 Data Converters DAC Design continued 2007 H K Page 10 R 2R Ladder DAC Opamp Offset Issue R out V in 1 Vos os R T ot al R RTotal If R T ota l l a r g e Vos out in Vos Vos Vout If RT ota l n o t l a rg e R out in 1 Vos Vos RT ot al P r ob l em Offset Model S i nce RT ota l i s co d e d ep en d an t ou t w ou l d b e co de d ep en da n t Vos G i ves r i s e t o I N L DN L EECS 247 Lecture 15 Data Converters DAC Design continued 2007 H K Page 11 R 2R Ladder Summary Advantages Resistor ratios only x2 Does not require precision capacitors Disadvantages Total device emitter area AEunitx 2B Not practical for high resolution DACs INL DNL error due to amplifier offset EECS 247 Lecture 15 Data Converters DAC Design continued 2007 H K Page 12 Static DAC Errors INL DNL Static DAC errors mainly due to component mismatch Systematic errors Contact resistance Edge effects in capacitor arrays Process gradients Finite current source output resistance Random variations Lithography etc Often Gaussian distribution central limit theorem Ref C Conroy et al Statistical Design Techniques for D A Converters JSSC Aug 1989 pp 1118 28 EECS 247 Lecture 15 Data Converters DAC Design continued 2007 H K Page 13 Current Source DAC DNL INL Due to Element Mismatch Iref Iref Iref Iref I Iref Vout Iref Iref I Simplified example 3 bit DAC Assume only two of the current sources mismatched 4 5 EECS 247 Lecture 15 Data Converters DAC Design continued 2007 H K Page 14 Current Source DAC DNL INL Due to Element Mismatch DN L m DN L 4 Analog Output seg men t m V L S B V LSB 7 Iref R seg men t 4 V L S B V LSB 6 5 I I R IR 4 IR DN L 4 I I LSB 3 I I R IR 2 DN L 5 IR 1xIref R DN L 5 I I L S B IN Lmax I I L S B EECS 247 Lecture 15 Digital Input 0 000 001 010 011 100 101 110 111 Data Converters DAC Design continued 2007 H K Page 15 Component Mismatch Probability Distribution Function Component parameters Random variables Each component is the product of many fabrication steps Most fabrication steps includes random variations Overall component variations product of several random variables Assuming each of these variables have a uniform distribution Joint pdf of a random variable affected by two uniformly distributed variables convolution of the two uniform pdfs pdf f x1 pdf f x2 pdf f x1 x2 pdf f x3 x4 pdf f x1 x2 EECS 247 Lecture 15 Gaussian pdf pdf f xm xn Data Converters DAC Design continued 2007 H K Page 16 p x 1 e 2 Probability density p x Gaussian Distribution 2 x 2 2 0 4 0 3 0 2 0 1 0 3 2 1 where is the expected value and standard deviation E X 2 2 0 1 x 2 3 2 variance EECS 247 Lecture 15 Data Converters DAC Design continued 2007 H K Page 17 P X x X 1 X e 2 X X e rf 2 EECS 247 Lecture 15 x 2 …
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