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Berkeley ELENG 247A - Lecture Notes

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EECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2007 H.K. Page 1EE247Lecture 15• Administrative issues Midterm exam postponed to Thurs. Oct. 25tho You can only bring one 8x11 paper with your own written notes (please do not photocopy)o No books, class or any other kind of handouts/notes, calculators, computers, PDA, cell phones....o Midterm includes material covered to end of lecture 14o Also, reading material including IEEE publications for Nyquist rate data converters posted EECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2007 H.K. Page 2EE247Lecture 15• D/A converters continued:– R-2R type DACs– Static performance of D/As• Component matching• Systematic & random errors– Practical aspects of current-switched DACs– Segmented current-switched DACs– DAC self calibration techniques• Current copiers• Dynamic element matchingEECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2007 H.K. Page 3Summary Last Lecture• Data Converters – Data converter testing (continued)• DNL & SNR, INL & SFDR• Effective number of bits (ENOB)– D/A converter architectures:• Resistor string DAC• Serial charge redistribution DAC• Parallel charge scaling DAC• Combination of resistor string (MSB) & binary weighted charge scaling (LSB)• Current source DAC– Unit element– Binary weightedEECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2007 H.K. Page 4R-2R Ladder Type DAC• R-2R DAC basics:– Simple R network divides both voltage & current by 2RVV/22R2RII/2I/2Increase # of bits by replicating circuitEECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2007 H.K. Page 5R-2R Ladder DACVB2R2REmitter-follower added to convert to high output impedance current sources2R2R2R2RRRRRVEEIoutEECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2007 H.K. Page 6R-2R Ladder DACHow Does it Work?VBConsider a simple 3bit R-2R DAC: 2R2R2R2RRRVEEIout1xAunit1xAunit2xAunit4xAunitEECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2007 H.K. Page 7R-2R Ladder DACHow Does it Work?VBSimple 3bit DAC:1- Consolidate first two stages: 2R2R2R2RRRVEEITI1I2I3AunitAunit2Aunit4AunitQTQ1Q2Q3VB2R2RRRRVEEI1+ITI2I32Aunit2Aunit4AunitQ2Q3EECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2007 H.K. Page 8R-2R Ladder DACHow Does it Work?Simple 3bit DAC-2- Consolidate next two stages:VB2R2RRRRVEEI1+ITI2I32Aunit2Aunit4AunitQ2Q3VB2RRRVEEI2+I1+ITI34Aunit4AunitQ2Q3Total Total Total321 3 2 1TIIIIIII I ,I ,I248=++→= = =EECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2007 H.K. Page 9R-2R Ladder DACHow Does it Work?VBConsider a simple 3bit R-2R DAC: 2R2R2R2RRRVEEII2I4I2I4IIoutAunitAunit2Aunit4AunitRef: B. Razavi, “Data Conversion System Design”, IEEE Press, 1995, page 84-87In most cases need to convert output current to voltageEECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2007 H.K. Page 10R-2R Ladder DACVB2R2RTrans-resistance amplifier added to:- Convert current to voltage- Generate virtual ground @ current summing node so that output impedance of current sources do not cause error- Issue: error due to opamp offsetVoutR-+2R2R2R2RRRRRVEEII2I4I8I16I2I4I8I16IRTotalEECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2007 H.K. Page 11R-2R Ladder DACOpamp Offset Issueout inos osTotalTotalout inos osTotalout inos osTotalTotaloutosR1VVRIf R large,VVIf R not largeR1VVRProblem:Since R is code dependant V would be code dependant Gives rise to INL & DNL⎛⎞+=⎜⎟⎝⎠=→≈=⎛⎞+→=⎜⎟⎝⎠→→VoutR-+RTotalosVOffsetModelEECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2007 H.K. Page 12R-2R LadderSummary• Advantages:– Resistor ratios only x2– Does not require precision capacitors• Disadvantages:– Total device emitter area Æ AEunitx 2BÆ Not practical for high resolution DACs– INL/DNL error due to amplifier offsetEECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2007 H.K. Page 13Static DAC Errors -INL / DNLStatic DAC errors mainly due to component mismatch– Systematic errors• Contact resistance• Edge effects in capacitor arrays• Process gradients• Finite current source output resistance– Random variations• Lithography etc…• Often Gaussian distribution (central limit theorem)*Ref: C. Conroy et al, “Statistical Design Techniques for D/A Converters,” JSSCAug. 1989, pp. 1118-28.EECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2007 H.K. Page 14Current Source DACDNL/INL Due to Element Mismatch • Simplified example:– 3-bit DAC– Assume only two of the current sources mismatched (# 4 & #5)IrefIrefIrefIrefIrefIref +ΔIIref -ΔIVout-+EECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2007 H.K. Page 15maxsegment[m] V[LSB]DNL[m]V[LSB]segment[4] V[LSB]DNL[4]V[LSB](I I)R IRIRDNL[4] I / I [LSB](I I)R IRDNL[5]IRDNL[5] I / I[LSB]INL I / I [LSB]−=−=−Δ −==−Δ+Δ −==Δ→=−Δ000 001 010 011 100 101 110 111DigitalInputAnalog Output 7 IrefR654321xIrefR0Current Source DACDNL/INL Due to Element Mismatch EECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2007 H.K. Page 16Component MismatchProbability Distribution Function• Component parameters Æ Random variables• Each component is the product of many fabrication steps• Most fabrication steps includes random variationsÆOverall component variations product of several random variablesÆAssuming each of these variables have a uniform distribution:ÆJoint pdf of a random variable affected by two uniformly distributed variables Æ convolution of the two uniform pdfs…….Æpdf [f(x1)]**pdf [f(x2)]pdf [f(x1,x2)]pdf [f(x1,x2)]pdf [f(x3,x4)]..……..pdf [f(xm,xn)]*ÆGaussian pdfEECS 247- Lecture 15 Data Converters:DAC Design (continued) © 2007 H.K. Page 17Gaussian Distribution-3 -2 -1 0 1 2 300.10.20.30.4(x-μ) /σProbability density p(x)()222x222variance is the expected value and1p( x ) e2where:standard deviation : E( X )μσμπσσμσ−−→==−EECS 247- Lecture 15 Data Converters:DAC Design


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Berkeley ELENG 247A - Lecture Notes

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