EE247 Lecture 21 ADC Converters Comparator design continued Comparator architecture examples Techniques to reduce flash ADC complexity Interpolating Folding Interpolating folding Multi Step ADCs Two step flash Pipelined ADCs Effect of sub ADC sub DAC gain stage non idealities on overall ADC performance EECS 247 Lecture 21 Nyquist Rate ADCs 2008 H K Page 1 CMOS Comparator Example Flash ADC 8bits 1 2LSB INL fs 15MHz Vref 3 8V LSB 15mV No offset cancellation Ref A Yukawa A CMOS 8 Bit High Speed A D Converter IC JSSC June 1985 pp 775 9 EECS 247 Lecture 21 Nyquist Rate ADCs 2008 H K Page 2 Comparator with Auto Zero Note Reference voltage input both differential Ref I Mehr and L Singer A 500 Msample s 6 Bit Nyquist Rate ADC for Disk Drive Read Channel Applications JSSC July 1999 pp 912 20 EECS 247 Lecture 21 Nyquist Rate ADCs 2008 H K Page 3 Flash ADC Comparator with Auto Zero Voffset VC VC VRe f VRe f VOffset Ref I Mehr and D Dalton A 500 Msample s 6 Bit Nyquist Rate ADC for Disk Drive Read Channel Applications JSSC July 1999 pp 912 20 EECS 247 Lecture 21 Nyquist Rate ADCs 2008 H K Page 4 Flash ADC Comparator with Auto Zero Voffset Vo Vo AP1 AP2 VIn VI n VC VC VOff s et S u b st i t u t i n g f o r VC VC f r o m p r evio u s c yc le Vo AP1 AP2 VIn VIn VRe f VRe f N o t e O f fs et i s ca n cel l ed d i f f er ence b et w een i np u t r ef er en ce es t a b l i s hed Ref I Mehr and D Dalton A 500 Msample s 6 Bit Nyquist Rate ADC for Disk Drive Read Channel Applications JSSC July 1999 pp 912 20 EECS 247 Lecture 21 Nyquist Rate ADCs 2008 H K Page 5 Flash ADC Using Comparator with Auto Zero Ref I Mehr and D Dalton A 500 Msample s 6 Bit Nyquist Rate ADC for Disk Drive Read Channel Applications JSSC July 1999 pp 912 20 EECS 247 Lecture 21 Nyquist Rate ADCs 2008 H K Page 6 Bipolar Comparator Example Used in 8bit 400Ms s 6bit 2Gb s flash ADC Signal amplification during 1 high latch operates when 1 low Input buffers suppress kick back input current Separate ground and supply buses for frontend preamp kickback noise reduction Preamp Latched Comparator Ref Y Akazawa et al A 400MSPS 8b flash AD conversion LSI IEEE International Solid State Circuits Conference vol XXX pp 98 99 February 1987 Ref T Wakimoto et al Si bipolar 2GS s 6b flash A D conversion LSI IEEE International Solid State Circuits Conference vol XXXI pp 232 233 February 1988 EECS 247 Lecture 21 Nyquist Rate ADCs 2008 H K Page 7 Auto Zero Implementation Ref I Mehr and L Singer A 55 mW 10 bit 40 Msample s Nyquist Rate CMOS ADC JSSC March 2000 pp 318 25 EECS 247 Lecture 21 Nyquist Rate ADCs 2008 H K Page 8 Comparator Example Pipelined ADC Application Variation on Yukawa latch used w o preamp Good for low resolution ADCs in this case 1 5bit stage for a pipeline Note M1 M2 M11 M12 operate in triode mode x M11 M12 added to vary comparator threshold Conductance at node X is sum of GM1 GM11 Ref T B Cho and P R Gray A 10 b 20 Msample s 35 mW pipeline A D converter IEEE Journal of Solid State Circuits vol 30 pp 166 172 March 1995 EECS 247 Lecture 21 Nyquist Rate ADCs 2008 H K Page 9 Comparator Example continued M1 M2 M11 M12 operate in triode mode with all having equal L Conductance of input devices G1 G2 Cox L Cox L G W1 VI1 Vt h W11 VR Vt h VVo1 o1 Vo2 W1 VI 2 Vt h W11 VR Vt h CoxW1 V V W11 V V R R I1 I 2 L W1 To 1st order for W1 W2 W11 W12 Vthlatch W11 W1 x VR where VR VR VR G1 G2 VR fixed W11 12 varied from comparator to comparator Eliminates need for resistive divider DAC Ref T B Cho and P R Gray A 10 b 20 Msample s 35 mW pipeline A D converter IEEE Journal of Solid State Circuits vol 30 pp 166 172 March 1995 EECS 247 Lecture 21 Nyquist Rate ADCs 2008 H K Page 10 Comparator Example Pipelined ADC Used in a pipelined ADC with digital correction No offset cancellation required Differential reference input M7 M8 operate in triode region Preamp gain 10 Input buffers suppress kick back 1 high Cs charged to VR 2B is also high current diverted to latch comparator output in hold mode 2 high Cs connected to S Hout comparator input VR S Hout current sent to preamp comparator in amplify mode Ref S Lewis et al A Pipelined 5 Msample s 9 bit Analog to Digital Converter IEEE JSSC NO 6 Dec 1987 EECS 247 Lecture 21 Nyquist Rate ADCs 2008 H K Page 11 Reducing Flash ADC Complexity E g 10 bit straight flash Input range 0 1V LSB 1mV Comparators 1023 with offset 1 2 LSB Input capacitance 1023 100fF 102pF Power 1023 3mW 3W High power dissipation large area high input cap Techniques to reduce complexity power dissipation Interpolation Folding Folding Interpolation Two step pipelining EECS 247 Lecture 21 Nyquist Rate ADCs 2008 H K Page 12 Interpolation Idea Reduce number of preamps instead interpolate between preamp outputs Reduced number of preamps Reduced input capacitance Reduced area power dissipation Same number of latches 2B 1 Important side benefit Decreased sensitivity to preamp offset Improved DNL EECS 247 Lecture 21 Nyquist Rate ADCs 2008 H K Page 13 Flash ADC Preamp Output Vin A2 A1 Preamp Output V 0 5 A2 Vref2 A1 Vref1 0 Zero crossings to be detected by latches at Vin 0 5 0 0 5 1 Vref1 EECS 247 Lecture 21 1 5 2 2 5 3 Vin Vref2 Nyquist Rate ADCs Vref1 1 Vref2 2 2008 H K Page 14 Simulink Model Vin 1 Vin Vi A2 Preamp2 2 Delta Vref2 2 Y A1 Preamp1 1 Delta Vref1 EECS 247 Lecture 21 Nyquist Rate ADCs 2008 H K Page 15 Preamp Output Differential Preamp Output 0 5 Differential output crossings Vin Vref1 1 Vref2 2 A2 A2 A1 A 1 0 0 5 0 0 5 1 1 5 2 2 5 3 A1 A2 0 5 A1 A2 0 0 5 0 0 5 1 EECS 247 Lecture 21 1 5 Vin 2 2 5 Note Additional crossing of A1 A2 A2 A1 A1 A2 A1 A2 cross zero at 3 Nyquist Rate ADCs Vref12 0 5 1 2 1 5 2008 H K Page 16 Interpolation in Flash ADC Half as many reference voltages and preamps Interpolation factor x2 Vin A2 Example For 10bit straight Flash ADC need 2B 1024 preamps compared 2B 1 512 …
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