EE247 Lecture 13 Data Converters Data converter testing continued Dynamic tests Spectral testing brief review Relationship between DNL SNR INL SFDR Effective number of bits ENOB D A converters Various Architectures Resistor string DACs Serial charge redistribution DACs Charge scaling DACs R 2R type DACs Current based DACs EECS 247 Lecture 13 Data Converters Testing DAC Design 2009 Page 1 Data Converter Testing So Far Data Converters Static Tests Measuring DNL INL continued Servo loop Code density testing histogram testing Dynamic tests Spectral testing Reveals ADC errors associated with dynamic behavior i e ADC performance as a function of frequency Direct Discrete Fourier Transform DFT based measurements utilizing sinusoidal signals DFT measurements including windowing EECS 247 Lecture 13 Data Converters Testing DAC Design 2009 Page 2 Spectral Testing DFT Considerations Integer Cycles versus Windowing Sinusoidal input with integer number of cycles within the observation window Signal energy for a single sinusoid falls into single DFT bin Requires careful choice of fin of cycles integer N cycles fs fin non integer Ideal for simulations Measurements need to lock fin to fs PLL not always possible Windowing No restrictions on fin no need to have the signal locked to fs Good for measurements w o having the capability to lock fin to fs Signal energy and its harmonics distributed over several DFT bins handle smeared out harmonics with care Requires more samples for a given accuracy Note that no windowing is equal to windowing with a rectangular window EECS 247 Lecture 13 Data Converters Testing DAC Design 2009 Page 3 Relationship INL SFDR SNDR ADC Transfer Curve Output Output Real INL Input Quadratic shaped transfer function Gives rise to even order harmonics EECS 247 Lecture 13 INL Input Cubic shaped transfer function Gives rise to odd order harmonics Data Converters Testing DAC Design 2009 Page 4 DNL LSB Frequency Spectrum versus INL DNL 0 0 03 Good DNL and poor INL suggests distortion INL LSB 2 1 0 1 2 EECS 247 Lecture 13 INL Not fully symmetric 100 200 300 400 500 600 700 800 900 1000 bin Data Converters Testing DAC Design 2009 Page 5 Relationship INL SFDR SNDR Nature of harmonics depend on shape of INL curve Rule of Thumb SFDR 20log 2B INL E g 1LSB INL 10b SFDR 60dB Beware this is of course only true under the same conditions at which the INL was taken i e typically low input signal frequency EECS 247 Lecture 13 Data Converters Testing DAC Design 2009 Page 6 SNR Degradation due to DNL Source Ion Opris Uniform quantization error pdf was assumed for ideal quantizer over the range of 2 Let s now add uniform DNL over 2 and repeat math Joint pdf for two uniform pdfs Triangular shape EECS 247 Lecture 13 Data Converters Testing DAC Design 2009 Page 7 SNR Degradation due to DNL To find total noise Integrate triangular pdf e2 2 1 e 0 2 e2 de 6 SNR 6 02 N 1 25 dB 3dB Compare to ideal quantizer e2 2 e2 2 de 2 12 SNR 6 02 N 1 76 dB Error associated with DNL reduces overall SNR EECS 247 Lecture 13 Data Converters Testing DAC Design 2009 Page 8 SNR Degradation due to DNL More general case Uniform quantization error 0 5 Uniform DNL error DNL LSB Convolution yields trapezoid shaped joint pdf Overall SQNR becomes SQNR EECS 247 Lecture 13 1 2 N 2 2 2 2 DNL2 12 3 Data Converters Testing DAC Design 2009 Page 9 SNR Degradation due to DNL Degradation in dB 1 8 SQNR deg 1 76 10 log 1 DNL2 12 3 Valid only for cases where with no missing codes 8 6 SNR Degradation 4 dB 2 0 EECS 247 Lecture 13 0 0 2 0 4 0 6 DNL LSB 0 8 Data Converters Testing DAC Design 1 2009 Page 10 Summary INL SFDR DNL SNR INL SFDR DNL SNR Type of distortion depends on shape of INL Assumptions DNL pdf uniform No missing codes Rule of Thumb 1 2 N 2 2 SFDR 20 log 2B INL SQNR 2 DNL2 12 3 E g 1LSB INL 10b SFDR 60dB EECS 247 Lecture 13 2 Data Converters Testing DAC Design 2009 Page 11 Uniform DNL of occurrences 250 200 150 100 50 0 0 5 0 4 0 3 0 2 0 1 0 0 1 0 2 0 3 0 4 0 5 DNL DNL distribution of 12 bit ADC test chip Not quite uniform EECS 247 Lecture 13 Data Converters Testing DAC Design 2009 Page 12 Effective Number of Bits ENOB Is a 12 bit converter with 68dB SNDR really a 12 bit converter Effective Number of Bits ENOB of bits of an ideal ADC with the same SQNR as the SNDR of the non ideal ADC ENOB SNDR 1 76dB 6 02dB 68 1 76 11 0Bits 6 02 Above ADC is a 12bit ADC with ENOB 11bits EECS 247 Lecture 13 Data Converters Testing DAC Design 2009 Page 13 ENOB At best we get ideal ENOB only for negligible thermal noise DNL INL Low noise design is costly 4x penalty in power per extra ENOB bit or 6dB extra SNDR Rule of thumb for good performance power tradeoff ENOB N 2 EECS 247 Lecture 13 Data Converters Testing DAC Design 2009 Page 14 ENOB Survey R H Walden Analog to digital converter survey and analysis IEEE J on Selected Areas in Communications pp 539 50 April 1999 EECS 247 Lecture 13 Data Converters Testing DAC Design 2009 Page 15 Converter Testing Practical Aspects Equipment requirements Pitfalls EECS 247 Lecture 13 Data Converters Testing DAC Design 2009 Page 16 Direct ADC DAC Test Device Under Test DUT Vin Signal Generator ADC DAC Vout Spectrum Analyzer Clock Generator Need a very good DAC be ware of sinc droop of the DAC Actually a good way to get started EECS 247 Lecture 13 Data Converters Testing DAC Design 2009 Page 17 Direct ADC DAC Test Device Under Test DUT Signal Generator Bandpass V in or Lowpass ADC DAC Notch Filter Filter Clock Generator Spectrum Analyzer Issues to beware of Linearity of the signal generator output has to be much better than ADC linearity Spectrum analyzer nonlinearities May need to build purchase filters to address one or both above problems Clock generator signal jitter EECS 247 Lecture 13 Data Converters Testing DAC Design 2009 Page 18 Example State Of The Art ADC 2001 0 35micron technology 3V Supply W Yang et al A 3 V 340 mW 14 b 75 Msample s CMOS ADC with 85 dB SFDR at Nyquist input IEEE J of Solid State Circuits Dec 2001 Testing a high performance converter may be just as challenging as designing it Key to success is to be aware of test setup and equipment limitations EECS 247 Lecture 13 Data Converters Testing DAC Design 2009 Page 19 Example ADC Spectral Tests SFDR SDR SNR Ref W Yang et al A 3 V 340 mW 14 b 75 Msample s CMOS ADC with 85 dB SFDR at Nyquist input IEEE J of Solid State Circuits Dec 2001 EECS 247 Lecture 13 Data Converters Testing …
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