EECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2009 Page 1EE247Lecture 13• Data Converters – Data converter testing (continued)• Dynamic tests– Spectral testing (brief review)– Relationship between: DNL & SNR, INL & SFDR• Effective number of bits (ENOB)• D/A converters: Various Architectures– Resistor string DACs (Serial charge redistribution DACs– Charge scaling DACs– R-2R type DACs– Current based DACsEECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2009 Page 2Data Converter Testing (So Far)• Data Converters – Static Tests:• Measuring DNL & INL (continued)–Servo-loop– Code density testing (histogram testing)– Dynamic tests:– Spectral testingÆ Reveals ADC errors associated with dynamic behavior i.e. ADC performance as a function of frequency• Direct Discrete Fourier Transform (DFT) based measurements utilizing sinusoidal signals• DFT measurements including windowingEECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2009 Page 3Spectral Testing: DFT ConsiderationsInteger Cycles versus Windowing• Sinusoidal input with integer number of cycles within the observation window:– Signal energy for a single sinusoid falls into single DFT bin– Requires careful choice of fin:• # of cycles Æ integer •N/cycles = fs/ finnon-integer– Ideal for simulations– Measurements Æ need to lock finto fs(PLL)- not always possible• Windowing– No restrictions on finÆ no need to have the signal locked to fsÆ Good for measurements w/o having the capability to lock finto fs– Signal energy and its harmonics distributed over several DFT bins –handle smeared-out harmonics with care!– Requires more samples for a given accuracy– Note that no windowing is equal to windowing with a rectangular window!EECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2009 Page 4Relationship INL & SFDR/SNDRADC Transfer CurveINLInputOutputQuadratic shaped transfer function:Æ Gives rise to evenorder harmonicsRealINLInputOutputCubic shaped transfer function:Æ Gives rise to oddorder harmonicsEECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2009 Page 5Frequency Spectrum versus INL & DNL-0.030DNL [LSB]100 200 300 400 500 600 700 800 9001000-2-1012bin #INL [LSB]Good DNL and poor INLsuggests distortion INLÆNot fully symmetricEECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2009 Page 6Relationship INL & SFDR/SNDR• Nature of harmonics depend on "shape" of INL curve• Rule of Thumb: SFDR ≅ 20log(2B/INL)– E.g. 1LSB INL, 10bÆ SFDR≅60dB• Beware, this is of course only true under the same conditions at which the INL was taken, i.e. typically low input signal frequencyEECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2009 Page 7SNR Degradation due to DNL• Uniform quantization error pdf was assumed for ideal quantizer over the range of: +/- Δ/2• Let's now add uniform DNL over +/- Δ/2 and repeat math...– Joint pdf for two uniform pdfs Æ Triangular shape[Source: Ion Opris]EECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2009 Page 8SNR Degradation due to DNL• To find total noise Æ Integrate triangular pdf:• Compare to ideal quantizer:ÆError associated with DNL reduces overall SNR6)1(22022Δ=Δ−=∫Δ+deeee3dB[dB] 25.102.6 −⋅=⇒NSNR1222/2/22Δ=Δ=∫Δ+Δ−deee[dB] 76.102.6 +⋅=⇒NSNREECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2009 Page 9SNR Degradation due to DNL• More general case:– Uniform quantization error ±0.5Δ– Uniform DNL error ± DNL [LSB]– Convolution yields trapezoid shaped joint pdf– Overall SQNR becomes:3122221222DNLSQNRN+Δ⎟⎟⎠⎞⎜⎜⎝⎛Δ=EECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2009 Page 10SNR Degradation due to DNL• Degradation in dB:0 0.2 0.4 0.6 0.8 102468SNRDegradation[dB]|DNL| [LSB]⎥⎥⎥⎥⎦⎤⎢⎢⎢⎢⎣⎡+−=312181log1076.1deg_2DNLSQNRValid only for cases where with no missing codesEECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2009 Page 11SummaryINL & SFDR - DNL & SNRINL & SFDR• Type of distortion depends on "shape" of INL • Rule of Thumb: SFDR ≅20 log(2B/INL)– E.g. 1LSB INL, 10bÆ SFDR≅60dBDNL & SNRAssumptions: • DNL pdf Æuniform• No missing codes3122221222DNLSQNRN+Δ⎟⎟⎠⎞⎜⎜⎝⎛Δ=EECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2009 Page 12Uniform DNL?• DNL distribution of 12-bit ADC test chip• Not quite uniform...-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5050100150200250DNL# of occurrencesEECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2009 Page 13Effective Number of Bits (ENOB)• Is a 12-bit converter with 68dB SNDR really a 12-bit converter?•Effective Number of Bits (ENOB)Æ # of bits of an ideal ADC with the same SQNR as the SNDR of the non-ideal ADC• Æ Above ADC is a 12bit ADC with ENOB=11bitsBits0.1102.676.168dB02.6dB76.1=−=−=SNDRENOBEECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2009 Page 14ENOB• At best, we get "ideal" ENOB only for negligible thermal noise, DNL, INL• Low noise design is costly Æ 4x penalty in power per extra(ENOB-) bit or 6dB extra SNDR• Rule of thumb for good performance /power tradeoff: ENOB > N-2EECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2009 Page 15ENOB SurveyR. H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. on Selected Areas in Communications, pp. 539-50, April 1999EECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2009 Page 16Converter Testing Practical Aspects• Equipment requirements• PitfallsEECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2009 Page 17Direct ADC-DAC Test• Need a very good DAC (be ware of sinc droop of the DAC)• Actually a good way to "get started"...VinVoutSpectrumAnalyzerSignalGeneratorClockGeneratorDevice Under Test (DUT)ADC DACEECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2009 Page 18Direct ADC-DAC Test• Issues to beware of:– Linearity of the signal generator output has to be much better than ADC linearity– Spectrum analyzer nonlinearitiesÆ May need to build/purchase filters to address one or both aboveproblems– Clock generator signal
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