EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 1EE247Lecture 19ADC Converters• Sampling (continued)– Sampling switch charge injection• Complementary switch• Use of dummy device• Bottom-plate switching– Track & hold circuits– T/H circuit incorporating gain & offset cancellation• ESD protection impact on converter performance• ADC architectures- Nyquist rate ADCs- Oversampled ADCsEECS 247 Lecture 19: Data Converters © 2005 H.K. Page 2Switch Charge InjectionComplementary Switch• In slow clock case if area of n & p devices are equal Æ effect of overlap capacitor for n & p devices to first order cancel (matching n & p width and ΔL)φ1φ1Bφ1φ1BVGtVHViVLEECS 247 Lecture 19: Data Converters © 2005 H.K. Page 3Switch Charge InjectionComplementary SwitchFast Clock• In fast clock case Offset cancelled for equal device width Input voltage dependant error worse!φ1φ1BVGtVHViVL()()()ch n n ox n H ith nth pch p p ox p i Lch pch nossoi osnoxn poxpsQWCLVVVVQWCLVVQ1QV2C CVV1 VWC L WC L12Cεε−−−−−−=−−=−−⎛⎞Δ≈ −⎜⎟⎜⎟⎝⎠=+++≈− ×EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 4Switch Charge InjectionDummy SwitchViVOCstVHViVLVGVGB• Dummy switch same L as main switch but half W • Main device clock goes low, dummy device goes high Æ dummy switch acquires same amount of channel charge main switch needs to lose• Effective only if exactly half of the charge transferred to M2 and requires good matching between clock fall/riseWM2=1/2WM1VGVGBM1M2EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 5Switch Charge InjectionBottom Plate Sampling• Switches M2 opened slightly earlier compared to M1Æ Injected charge by the opening of M2 is constant & eliminated when used differentially• Since Csbottom plate open when M1 openedÆ no charge injected on Csφ1aVHVLtφ1bViVOM1φ1bφ1aM2CsEECS 247 Lecture 19: Data Converters © 2005 H.K. Page 6Flip-Around Track & HoldvINvOUTCS1Aφ1DS2φ2S2Aφ2S3φ1Dφ1S1vCMφ1φ1Dφ2• Concept based on bottom-plate samplingEECS 247 Lecture 19: Data Converters © 2005 H.K. Page 7Flip-Around T/H-Basic Operationφ1ÆhighvINvOUTCS1Aφ1DS2φ2S2Aφ2S3φ1Dφ1S1vCMCharging Cφ1φ1Dφ2EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 8Flip-Around T/H-Basic Operationφ2ÆhighvINvOUTCS1Aφ1DS2φ2S2Aφ2S3φ1Dφ1S1vCMHoldingφ1φ1Dφ2EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 9Flip-Around T/H - TimingvINvOUTCS1Aφ1DS2φ2S2Aφ2S3φ1Dφ1S1vCMSamplingS1 opens earlier than S1A "Bottom Plate Sampling"φ1φ1Dφ2EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 10Charge Injection• At the instant of sampling, some of the charge stored in sampling switch S1 is dumped onto C• With "Bottom Plate Sampling", charge injection comes only from S1 and is to first-order independent of vIN– Only a dc offset is added This dc offset can be removed with a differential architectureEECS 247 Lecture 19: Data Converters © 2005 H.K. Page 11Flip-Around T/HvINvOUTCS1Aφ1DS2φ2S2Aφ2S3φ1Dφ1S1vCMConstant switch VGSto minimize distortionφ1φ1Dφ2EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 12Flip-Around T/H• S1 is an n-channel MOSFET• Since it always switches the same voltage, it’s on-resistance, RS1, is signal-independent (to first order) • Choosing RS1>> RS1Aminimizes the non-linear component of R = RS1A+ RS1– S1A is a wide (much lower resistance than S1) & constant VGSswitch– In practice size of S1A is limited by the (nonlinear) S/D capacitance that also adds distortion– If S1A’s resistance is negligible Æ delay depends only on S1 resistance– S1 resistance is independent of VIN Æ delay is independent of VINEECS 247 Lecture 19: Data Converters © 2005 H.K. Page 13Differential Flip-Around T/HRef: W. Yang, et al. “A 3-V 340-mW 14-b 75-Msample/s CMOS ADC With 85-dB SFDRat Nyquist Input,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001 1931Offset voltage associated with charge injection of S11 & S12 cancelled by differential nature of the circuitS11S12EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 14Differential Flip-Around T/H• Gain=1• Feedback factor=1• ΔVin-cm=Vout_com-Vsig_com Æ Amplifier needs to have large input common-mode complianceφ1’φ1φ2EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 15Differential Flip-Around T/HChoice of Sampling Switch SizeRef: K. Vleugels et al, “A 2.5-V Sigma–Delta Modulator for Broadband Communications Applications “ IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001, pp. 1887•THD simulated w/o sampling switch boosted clock Æ -45dB•THD simulated with sampling switch boosted clock (see figure)EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 16Input Common-Mode CancellationRef: R. Yen, et al. “A MOS Switched-Capacitor Instrumentation Amplifier,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-17, NO. 6,, DECEMBER 1982 1008EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 17Input Common-Mode CancellationTrack mode (φ high)VC1=VI1, VC2=VI2Vo1=Vo2=0Hold mode (φ low)Vo1+Vo2=0Vo1-Vo2= -(VI1-VI2)(C1/(C1+C3))Æ Input common-mode level removedEECS 247 Lecture 19: Data Converters © 2005 H.K. Page 18Differential T/H Combined with Gain StageRef: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987Employs the previously discussed technique to eliminate the problem associated with high common-mode voltage excursion at the input of the opampEECS 247 Lecture 19: Data Converters © 2005 H.K. Page 19Ref: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987Differential T/H Combined with Gain StageEECS 247 Lecture 19: Data Converters © 2005 H.K. Page 20Ref: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987• Gain=4C/C=4• Feedback factor =1/(1+G)=0.2• Input voltage common-mode level removed• Amplifier offset not removedDifferential T/H Combined with Gain StageEECS 247 Lecture 19: Data Converters © 2005 H.K. Page 21Ref: H. Ohara, et al., "A CMOS programmable self-calibrating 13-bit eight-channel data acquisition peripheral," IEEE Journal of Solid-State Circuits, vol. 22, pp. 930 - 938, December 1987. • Operation during offset cancellation phase shown• Auxilary inputs added with
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