EE247 Lecture 19 ADC Converters Sampling continued Sampling switch charge injection Complementary switch Use of dummy device Bottom plate switching Track hold circuits T H circuit incorporating gain offset cancellation ESD protection impact on converter performance ADC architectures Nyquist rate ADCs Oversampled ADCs EECS 247 Lecture 19 Data Converters 2005 H K Page 1 Switch Charge Injection Complementary Switch 1 VG VH Vi 1B VL t 1 1B In slow clock case if area of n p devices are equal effect of overlap capacitor for n p devices to first order cancel matching n p width and L EECS 247 Lecture 19 Data Converters 2005 H K Page 2 Switch Charge Injection Complementary Switch Fast Clock VG Qc h n WnCo x Ln VH Vi Vth n VH Qc h p WpCo x Lp Vi VL Vt h p Vi 1 Q Q Vo c h p c h n 2 Cs Cs VL t Vo Vi 1 Vos 1 1 W C L WpCo x Lp n ox n 2 Cs 1B In fast clock case Offset cancelled for equal device width Input voltage dependant error worse EECS 247 Lecture 19 Data Converters 2005 H K Page 3 Switch Charge Injection Dummy Switch VG Vi M1 VGB VO M2 WM2 1 2WM1 Cs VH VG VGB Vi VL t Dummy switch same L as main switch but half W Main device clock goes low dummy device goes high dummy switch acquires same amount of channel charge main switch needs to lose Effective only if exactly half of the charge transferred to M2 and requires good matching between clock fall rise EECS 247 Lecture 19 Data Converters 2005 H K Page 4 Switch Charge Injection Bottom Plate Sampling 1a 1b VH M1 VO Vi VL 1b Cs 1a M2 t Switches M2 opened slightly earlier compared to M1 Injected charge by the opening of M2 is constant eliminated when used differentially Since Cs bottom plate open when M1 opened no charge injected on Cs EECS 247 Lecture 19 Data Converters 2005 H K Page 5 Flip Around Track Hold 2 S2A 1D vIN C 2 1D S3 1 S1 vCM EECS 247 Lecture 19 Data Converters 1D 2 vOUT S2 S1A 1 Concept based on bottomplate sampling 2005 H K Page 6 Flip Around T H Basic Operation 1 high 2 S2A 1 1D 1D 2 1D vIN C 2 S3 vOUT S2 S1A 1 Charging C S1 vCM EECS 247 Lecture 19 Data Converters 2005 H K Page 7 Flip Around T H Basic Operation 2 high 2 1 S2A 1D vIN C 2 1D S3 1 2 Holding vOUT S2 S1A 1D S1 vCM EECS 247 Lecture 19 Data Converters 2005 H K Page 8 Flip Around T H Timing 2 S2A 1D vIN C 2 1 1D S3 1 2 Sampling vOUT S2 S1A 1D S1 vCM S1 opens earlier than S1A Bottom Plate Sampling EECS 247 Lecture 19 Data Converters 2005 H K Page 9 Charge Injection At the instant of sampling some of the charge stored in sampling switch S1 is dumped onto C With Bottom Plate Sampling charge injection comes only from S1 and is to first order independent of vIN Only a dc offset is added This dc offset can be removed with a differential architecture EECS 247 Lecture 19 Data Converters 2005 H K Page 10 Flip Around T H 2 Constant switch VGS to minimize distortion S2A 1D vIN C 2 1D S3 1 1D 2 vOUT S2 S1A 1 S1 vCM EECS 247 Lecture 19 Data Converters 2005 H K Page 11 Flip Around T H S1 is an n channel MOSFET Since it always switches the same voltage it s onresistance RS1 is signal independent to first order Choosing RS1 RS1A minimizes the non linear component of R RS1A RS1 S1A is a wide much lower resistance than S1 constant VGS switch In practice size of S1A is limited by the nonlinear S D capacitance that also adds distortion If S1A s resistance is negligible delay depends only on S1 resistance S1 resistance is independent of VIN delay is independent of VIN EECS 247 Lecture 19 Data Converters 2005 H K Page 12 Differential Flip Around T H S11 S12 Offset voltage associated with charge injection of S11 S12 cancelled by differential nature of the circuit Ref W Yang et al A 3 V 340 mW 14 b 75 Msample s CMOS ADC With 85 dB SFDR at Nyquist Input IEEE JOURNAL OF SOLID STATE CIRCUITS VOL 36 NO 12 DECEMBER 2001 1931 EECS 247 Lecture 19 Data Converters 2005 H K Page 13 Differential Flip Around T H 1 1 2 Gain 1 Feedback factor 1 Vin cm Vout com Vsig com Amplifier needs to have large input common mode compliance EECS 247 Lecture 19 Data Converters 2005 H K Page 14 Differential Flip Around T H Choice of Sampling Switch Size THD simulated w o sampling switch boosted clock 45dB THD simulated with sampling switch boosted clock see figure Ref K Vleugels et al A 2 5 V Sigma Delta Modulator for Broadband Communications Applications IEEE JOURNAL OF SOLID STATE CIRCUITS VOL 36 NO 12 DECEMBER 2001 pp 1887 EECS 247 Lecture 19 Data Converters 2005 H K Page 15 Input Common Mode Cancellation Ref R Yen et al A MOS Switched Capacitor Instrumentation Amplifier IEEE JOURNAL OF SOLID STATE CIRCUITS VOL SC 17 NO 6 DECEMBER 1982 1008 EECS 247 Lecture 19 Data Converters 2005 H K Page 16 Input Common Mode Cancellation Track mode high VC1 VI1 VC2 VI2 Vo1 Vo2 0 Hold mode low Vo1 Vo2 0 Vo1 Vo2 VI1 VI2 C1 C1 C3 Input common mode level removed EECS 247 Lecture 19 Data Converters 2005 H K Page 17 Differential T H Combined with Gain Stage Employs the previously discussed technique to eliminate the problem associated with high common mode voltage excursion at the input of the opamp Ref S H Lewis et al A Pipelined 5 Msample s 9 bit Analog to Digital Converter IEEE JSSC VOL SC 22 NO 6 DECEMBER 1987 EECS 247 Lecture 19 Data Converters 2005 H K Page 18 Differential T H Combined with Gain Stage Ref S H Lewis et al A Pipelined 5 Msample s 9 bit Analog to Digital Converter IEEE JSSC VOL SC 22 NO 6 DECEMBER 1987 EECS 247 Lecture 19 Data Converters 2005 H K Page 19 Differential T H Combined with Gain Stage Gain 4C C 4 Feedback factor 1 1 G 0 2 Input voltage common mode level removed Amplifier offset not removed Ref S H Lewis et al A Pipelined 5 Msample s 9 bit Analog to Digital Converter IEEE JSSC VOL SC 22 NO 6 DECEMBER 1987 EECS 247 Lecture 19 Data Converters 2005 H K Page 20 Differential T H Including Offset Cancellation Operation during offset cancellation phase shown Auxilary inputs added with Amain Aaux 10 Ref H Ohara et al A CMOS programmable self calibrating 13 bit eight channel data acquisition peripheral IEEE Journal of Solid State Circuits vol 22 pp 930 938 December 1987 EECS 247 Lecture 19 Data Converters 2005 H K Page …
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