EE247 Lecture 25 Administrative EE247 Final exam Date Sat Dec 13th Time 5 to 8pm Location 203 MCL same as class Closed course notes books No calculators cell phones PDAs computers Bring two 8x11 paper with your own notes Final exam covers the entire course material unless specified otherwise EECS 247 Lecture 25 Oversampled ADCs 2008 H K Page 1 EE247 Lecture 25 Oversampled ADCs continued 2nd order modulator Practical implementation Effect of various building block nonidealities on the performance Integrator maximum signal handling capability Integrator finite DC gain Comparator hysteresis Integrator non linearity Effect of KT C noise Finite opamp bandwidth Opamp slew limited settling Implementation example Higher order modulators Cascaded modulators multi stage Single loop single quantizer modulators with multi order filtering in the forward path EECS 247 Lecture 25 Oversampled ADCs 2008 H K Page 2 2nd Order Modulator Example Digital audio application Signal bandwidth 20kHz Desired resolution 16 bit 16 bit 98 dB Dynamic Range DR 2 nd order 11 1dB 50 log M M min 153 M 256 28 DR 109dB two reasons 1 Allow some margin so that thermal noise dominate provides dithering to minimize level of in band limit cycle oscillation 2 Choice of M power of 2 ease of digital filter implementation Sampling rate 2x20kHz 5kHz M 12MHz quite reasonable EECS 247 Lecture 25 Oversampled ADCs 2008 H K Page 3 Limit Cycle Tones in 1st Order 2nd Order Modulator Higher oversampling ratio lower tones 6dB 1st Order Modulator 2nd order tones much lower compared to 1st 2X increase in M decreases the tones by 6dB for 1st order loop and 12dB for 2nd order loop 12dB 2nd Order Modulator Inband Quantization noise Ref B P Brandt et al Second order sigma delta modulation for digital audio signal acquisition IEEE Journal of Solid State Circuits vol 26 pp 618 627 April 1991 R Gray Spectral analysis of quantization noise in a single loop sigma delta modulator with dc input IEEE Trans Commun vol 37 pp 588 599 June 1989 EECS 247 Lecture 25 Oversampled ADCs 2008 H K Page 4 Implementation Practical Design Considerations Internal node scaling clipping Effect of finite opamp gain linearity KT C noise Opamp noise Effect of comparator nonidealities Power dissipation considerations EECS 247 Lecture 25 Oversampled ADCs 2008 H K Page 5 Switched Capacitor Implementation 2nd Order Nodes Scaled for Maximum Dynamic Range Modification gain of in front of integrators reduce optimize required signal range at the integrator outputs 1 7x input full scale Note Non idealities associated with 2nd integrator and quantizer when referred to the input is attenuated by 1st integrator high gain The only building block requiring low noise and high accuracy is the 1st integrator Ref B E Boser and B A Wooley The Design of Sigma Delta Modulation A D Converters IEEE J Solid State Circuits vol 23 no 6 pp 1298 1308 Dec 1988 EECS 247 Lecture 25 Oversampled ADCs 2008 H K Page 6 2nd Order Modulator Example Switched Capacitor Implementation Dout VIN Fully differential front end Two bottom plate integrators 1 bit DAC is made of switches and Vrefs EECS 247 Lecture 25 Oversampled ADCs 2008 H K Page 7 Switched Capacitor Implementation 2nd Order Phase 1 Dout VIN During phase 1 1st integrator samples Vin on 1st stage C1 2nd integrator samples output of 1st integrator Comparator senses polarity of 2nd intg output result saved in output latch S3 opens prior to S1 minimize effect of charge injection EECS 247 Lecture 25 Oversampled ADCs 2008 H K Page 8 Switched Capacitor Implementation 2nd Order Phase 2 Dout VIN Note S2 connects integrator inputs to or Vref polarity depends on whether Dout is 0 or 1 Input sampled during 1 or C1xVref transferred to C2 DAC output subtraction integration EECS 247 Lecture 25 Oversampled ADCs 2008 H K Page 9 2nd Order Modulator Switched Capacitor Implementation The loss in front of each integrator implemented by choice of C2 2C1 EECS 247 Lecture 25 f0intg fs 4 Oversampled ADCs 2008 H K Page 10 Design Phase Simulations Design of oversampled ADCs requires simulation of extremely long data traces due to the oversampled nature of the system SPICE type simulators Normally used to test for gross circuit errors only Too slow for detailed performance verification Typically behavioral modeling is used in MATLAB like environments Circuit non idealities either computed or found by using SPICE at subcircuit level Non idealities introduced in the behavioral model one by one first to fully understand the effect of each individually Next step is to add as many of the non idealities simultaneously as possible to verify whether there are interaction among non idealities EECS 247 Lecture 25 Oversampled ADCs 2008 H K Page 11 Example Testing ADC Note The Nyquist ADC tests such as INL and DNL test do not apply to modulator type ADCS 2nd order M 256 t aly An l ica e ur as e M d testing is performed via SNDR as a function of input signal level EECS 247 Lecture 25 Oversampled ADCs 2008 H K Page 12 2nd Order Effect of 1st Integrator Maximum Signal Handling Capability on SNR M 256 Behavioral model Non idealities tested one by one 1st integrator maximum signal handling 1 4 1 5 1 6 and 1 7X Effect of 1st Integrator maximum signal handling capability on converter SNR No SNR loss for max sig handling 1 7 Ref B E Boser et al The Design of Sigma Delta Modulation A D Converters JSSC Dec 1988 EECS 247 Lecture 25 Oversampled ADCs 2008 H K Page 13 2nd Order Effect of 2nd Integrator Maximum Signal Handling Capability on SNR 2nd integrator maximum signal handling 0 75 1 1 25 1 5 and 1 7X Effect of 2nd Integrator maximum signal handling capability on SNR SNR loss for max sig handling 1 7 Ref B E Boser et al The Design of Sigma Delta Modulation A D Converters JSSC Dec 1988 EECS 247 Lecture 25 Oversampled ADCs 2008 H K Page 14 2nd Order Effect of Integrator Finite DC Gain Integrator 1 CI 2 Cs a Vi Cs z 1 CI 1 z 1 1 a z Cs 1 a Cs CI H z Finit DC Gain CI 1 a 1 z 1 Cs 1 a CI H DC a H z ideal Vo a opamp gain at DC EECS 247 Lecture 25 Oversampled ADCs 2008 H K Page 15 2nd Order Effect of Integrator Finite DC Gain l o g H s Ideal Integ a infinite eQ DOUT a H 0 0 P1 a Integrator magnitude response Note Quantization transfer function wrt output has integrator in the feedback path EECS 247 Lecture 25 Dout 1 eQ 1 H D C for ide al inte g D o ut 0 eQ D ou t 1 D C for real integ eQ a Oversampled ADCs 2008 H K Page 16 1st 2nd Order Effect of Integrator Finite DC Gain Max signal level a f0 a Low
View Full Document
Unlocking...