EECS 247 Lecture 25 Oversampled ADCs © 2008 H.K. Page 1EE247Lecture 25• Administrative–EE247 Final exam: – Date: Sat. Dec.13th– Time: 5 to 8pm– Location: 203 MCL (same as class)• Closed course notes/books• No calculators/cell phones/PDAs/computers• Bring two 8x11 paper with your own notes• Final exam covers the entire course material unless specified otherwiseEECS 247 Lecture 25 Oversampled ADCs © 2008 H.K. Page 2EE247Lecture 25Oversampled ADCs (continued)–2ndorder ΣΔ modulator• Practical implementation– Effect of various building block nonidealities on the ΣΔperformance• Integrator maximum signal handling capability • Integrator finite DC gain • Comparator hysteresis • Integrator non-linearity • Effect of KT/C noise• Finite opamp bandwidth• Opamp slew limited settling– Implementation example–Higher order ΣΔ modulators• Cascaded modulators (multi-stage)• Single-loop single-quantizer modulators with multi-order filtering in the forward pathEECS 247 Lecture 25 Oversampled ADCs © 2008 H.K. Page 32ndOrder ΣΔ Modulator ExampleM Æ256=28(ÆDR=109dB) two reasons:1. Allow some margin so that thermal noise dominate & provides dithering to minimize level of in-band limit cycle oscillation2. Choice of M power of 2 Æ ease of digital filter implementation Æ Sampling rate (2x20kHz + 5kHz)M = 12MHz (quite reasonable!)• Digital audio application• Signal bandwidth 20kHz• Desired resolution 16-bit2 Dynamic Range50nd ordermin16 bit 98 dBDR -11.1dB log MM 153ΣΔ−→=+=EECS 247 Lecture 25 Oversampled ADCs © 2008 H.K. Page 4Limit Cycle Tones in 1stOrder & 2ndOrder ΣΔ Modulator• Higher oversampling ratio Æ lower tones•2ndorder tones much lower compared to 1st•2Xincrease in M decreases the tones by 6dB for 1storder loop and 12dB for 2ndorder loopRef: B. P. Brandt, et al., "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp. 618 - 627, April 1991.R. Gray, “Spectral analysis of quantization noise in a single-loop sigma–delta modulator with dc input,” IEEE Trans. Commun., vol. 37, pp. 588–599, June 1989.6dB12dB2ndOrder ΣΔ Modulator1stOrder ΣΔ ModulatorInband Quantization noiseEECS 247 Lecture 25 Oversampled ADCs © 2008 H.K. Page 5ΣΔ ImplementationPractical Design Considerations• Internal node scaling & clipping• Effect of finite opamp gain & linearity• KT/C noise• Opamp noise• Effect of comparator nonidealities• Power dissipation considerationsEECS 247 Lecture 25 Oversampled ADCs © 2008 H.K. Page 6Switched-Capacitor Implementation 2ndOrder ΣΔNodes Scaled for Maximum Dynamic Range• Modification (gain of ½ in front of integrators) reduce & optimize required signal range at the integrator outputs ~ 1.7x input full-scale (Δ)• Note: Non-idealities associated with 2ndintegrator and quantizer when referred to the ΣΔ input is attenuated by 1stintegrator high gainÆ The only building block requiring low-noise and high accuracy is the 1stintegratorRef: B.E. Boser and B.A. Wooley, “The Design of Sigma-Delta Modulation A/D Converters,”IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1298-1308, Dec. 1988.EECS 247 Lecture 25 Oversampled ADCs © 2008 H.K. Page 72ndOrder ΣΔ ModulatorExample: Switched-Capacitor ImplementationVINDout• Fully differential front-end• Two bottom-plate integrators• 1-bit DAC is made of switches and VrefsEECS 247 Lecture 25 Oversampled ADCs © 2008 H.K. Page 8VINDoutDuring phase 1:•1stintegrator samples Vin on 1ststage C1•2ndintegrator samples output of 1stintegrator• Comparator senses polarity of 2ndintg. output Æ result saved in output latch• S3 opens prior to S1 Æ minimize effect of charge injectionSwitched-Capacitor Implementation 2ndOrder ΣΔPhase 1EECS 247 Lecture 25 Oversampled ADCs © 2008 H.K. Page 9Switched-Capacitor Implementation 2ndOrder ΣΔPhase 2VINDout• Note: S2 connects integrator inputs to + or – Vref, polarity depends on whether Dout is 0 or 1• Input sampled during φ1– or + C1xVref transferred to C2 Æ DAC output subtraction & integration EECS 247 Lecture 25 Oversampled ADCs © 2008 H.K. Page 102ndOrder ΣΔ ModulatorSwitched-Capacitor ImplementationC2=2C1• The ½ loss in front of each integrator implemented by choice of:Æf0intg=fs /(4π)EECS 247 Lecture 25 Oversampled ADCs © 2008 H.K. Page 11Design Phase Simulations• Design of oversampled ADCs requires simulation of extremely long data traces due to the oversampled nature of the system• SPICE type simulators:– Normally used to test for gross circuit errors only – Too slow for detailed performance verification• Typically, behavioral modeling is used in MATLAB-like environments• Circuit non-idealities either computed or found by using SPICE at subcircuit level • Non-idealities introduced in the behavioral model one-by-one first to fully understand the effect of each individually• Next step is to add as many of the non-idealities simultaneously as possible to verify whether there are interaction among non-idealitiesEECS 247 Lecture 25 Oversampled ADCs © 2008 H.K. Page 12Example: Testing ΣΔ ADC2ndorder ΣΔM=256AnalyticalMeasuredNote: The Nyquist ADC tests such as INL and DNL test do not apply to ΣΔmodulator type ADCSΣΔ testing is performed via SNDR as a function of input signal levelEECS 247 Lecture 25 Oversampled ADCs © 2008 H.K. Page 132ndOrder ΣΔEffect of 1stIntegrator Maximum Signal Handling Capability on SNR1stintegrator maximum signal handling:1.4, 1.5,1.6, and 1.7X Δ• Effect of 1stIntegrator maximum signal handling capability on converter SNRÆ No SNR loss for max. sig. handling >1.7ΔRef: B.E. Boser et. al, “The Design of Sigma-Delta Modulation A/D Converters,” JSSC, Dec. 1988.M=256– Behavioral model – Non-idealities tested one by oneEECS 247 Lecture 25 Oversampled ADCs © 2008 H.K. Page 142ndOrder ΣΔEffect of
View Full Document