Digital Filters Advantages of digital filters Dynamic range No coefficient errors aging Programmable Always work on first silicon if FIR filters Linear phase Synthesis FIR IIR comparison Implementation issues Coefficient rounding Intermediate result dynamic range Limit cycles A D DSP EECS 247 Lecture 11 Digital Filters 2002 B Boser 1 Analog versus Digital DR It s much less expensive to add dynamic range to digital circuits than analog circuits To double the dynamic range of a digital datapath we need to add only a bit to an already wide datapath 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 3 2 1 0 6dB DR 16 15 14 13 12 11 10 9 A D DSP EECS 247 Lecture 11 Digital Filters 8 7 6 5 2002 B Boser 2 Analog versus Digital DR For comparison consider summing the outputs of 4 identical analog circuits with identical inputs vIN A1 A2 A3 A4 vOUT A D DSP EECS 247 Lecture 11 Digital Filters 2002 B Boser 3 Analog versus Digital DR Analog noise is typically uncorrelated in each of the blocks A1 A4 vIN A1 A2 Signal grows 4X Noise grows 2X 6dB Dynamic Range A D DSP EECS 247 Lecture 11 Digital Filters A3 A4 vOUT 2002 B Boser 4 Analog versus Digital DR Doubling analog DR is very expensive 4X the power 4X the area Doubling digital DR is relatively cheap And cost function decreases by 29 year 3dB year Practical circuits tolerate very little loss of DR due to finite datapath precision in their DSP sections Analog dynamic range is too precious to lose Digital DR loss of 5 0 4dB of total noise power is typical Why use analog filters at all A D DSP EECS 247 Lecture 11 Digital Filters 2002 B Boser 5 The figure shows the DR of the best standalone ADCs in 2000 Dynamic range decreases as converter bandwidth increases From 1975 1995 ADC performance at any sampling frequency improved by 2dB year A D DSP EECS 247 Lecture 11 Digital Filters Dynamic Range dB Bits ADC Dynamic Range 140 23 120 20 100 16 80 13 60 10 40 6 20 3 104 108 106 ADC Sampling Frequency Hz 2002 B Boser 6 ADC Dynamic Range ADCs embedded in IC Systems on a Chip SoCs have less DR than the best standalone ADCs The embedded ADC performance level is shown in red Analog digital crosstalk and design risk issues limit embedded ADC DR to about 100dB Dynamic Range dB 140 1 GHz 30dB DR levels are much more forgiving and the performance gap narrows A D DSP 120 100 80 60 40 embedded ADCs 20 104 108 106 ADC Sampling Frequency Hz EECS 247 Lecture 11 Digital Filters 2002 B Boser 7 ADC Dynamic Range 140 Minimization of analog signal processing is a key goal of mixed signal IC architecture However analog signal processing is almost unavoidable above the red line Dynamic Range dB 120 100 80 60 40 embedded ADCs 20 104 108 106 ADC Sampling Frequency Hz A D DSP EECS 247 Lecture 11 Digital Filters 2002 B Boser 8 Practical Constraints Only few ADC design teams in the world can produce green line dynamic range If your SoC architecture requires one of those teams to succeed think again Mixed signal SoC architectures fail when their architects choose to ignore long established empirically proven performance scaling laws A D DSP EECS 247 Lecture 11 Digital Filters 2002 B Boser 9 FIR Filters Only finite zeros Linear phase if coefficients are symmetric Implement with delays multipliers adders Lack of good analog delays prevents widespread use of analog FIR filters Good synthesis tools e g Remez Exchange algorithm A D DSP EECS 247 Lecture 11 Digital Filters 2002 B Boser 10 FIR Filter Phase Response Consider the Nth order FIR filter with transfer function H z a0 a1z 1 a2z 2 aN 2z2 N aN 1z1 N aNz N Suppose the filter coefficients are symmetric about the middle term i e H z a0 a1z 1 a2z 2 a2z2 N a1z1 N a0z N A D DSP EECS 247 Lecture 11 Digital Filters 2002 B Boser 11 FIR Filter Phase Response H z a0 a1z 1 a2z 2 a2z2 N a1z1 N a0z N a0 1 z N a1 z 1 z1 N a2 z 2 z2 N a0z N 2 zN 2 z N 2 a1z N 2 z 1 N 2 z1 N 2 a2z N 2 z 2 N 2 z2 N 2 z N 2 a0 zN 2 z N 2 a1 z 1 N 2 z1 N 2 a2 z 2 N 2 z2 N 2 A D DSP EECS 247 Lecture 11 Digital Filters 2002 B Boser 12 FIR Filter Phase Response The term in brackets is a sum of cosine terms with no phase shift H ej T e j NT 2 2a0cos NT 2 more real cos terms The constant group delay of the symmetric coefficient FIR filter is obvious NT 2 GR NT 2 half the filter impulse response duration A D DSP EECS 247 Lecture 11 Digital Filters 2002 B Boser 13 Coefficient Symmetry Three classes of zero groupings produce symmetric coefficients and linear phase The first is real axis zeroes at r and 1 r H z z 2 r 1 r z 1 1 A D DSP EECS 247 Lecture 11 Digital Filters 2002 B Boser 14 Coefficient Symmetry Conjugate pairs of unit circle zeroes provide linear phase H z z 2 2z 1cos 1 A D DSP EECS 247 Lecture 11 Digital Filters 2002 B Boser 15 Coefficient Symmetry Finally groups of four zeroes at re j and 1 r e j provide linear phase The filter coefficients for these 4 zeroes are 1 2 r 1 r cos 4 r2 1 r2 2 r 1 r cos 1 A D DSP EECS 247 Lecture 11 Digital Filters 2002 B Boser 16 FIR Filter Phase Response Another interesting case involves antisymmetric filter coefficients H z a0 a1z 1 a2z 2 a2z2 N a1z1 N a0z N It s easy to show that H ej T e j NT 2ej 2 2a0sin NT 2 more sin terms A D DSP EECS 247 Lecture 11 Digital Filters 2002 B Boser 17 FIR Filter Phase Response For the antisymmetric coefficient case NT 2 2 GR NT 2 It s still linear phase but with the frequency independent 90 phase shift characteristic of differentiators A D DSP EECS 247 Lecture 11 Digital Filters 2002 B Boser 18 Linear Phase FIR Example fs 1e6 Fp 0 10 fs Fs 0 13 fs Rp 0 1 Rs 60 x 10 Rp 20 1 10 Rp 20 1 y 10 Rs 20 0 N fo ao W remezord 10 Fp Fs 1 0 x y fs 20 b remez N fo ao W 30 Hr tf b 1 1 fs 40 Hr Hr 10 rpass 40 0 Magnitude dB 0 02 0 04 0 06 0 08 0 1 0 12 2 4 6 Frequency 0 f 2 Hz s 8 10 4 x 10 Magnitude dB …
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