EECS 247 Lecture 24: Multi-Rate Filters © 2002 B. Boser 1A/DDSPToday’s Lecture• Modeling the Σ∆ ADC decimation filter– Decimated DFTs– Fixed and floating point comparisons– Troubleshooting and test modes• Multistage decimation filters– Parks-McClellan filters– Manual decimators– Hogenauer filters– Half-band filtersEECS 247 Lecture 24: Multi-Rate Filters © 2002 B. Boser 2A/DDSPFilter #2 Responses[kHz]Decimation Filter Gain [dB]120800-40160400 40302010 50floating point coefficients23b coefficientsEECS 247 Lecture 24: Multi-Rate Filters © 2002 B. Boser 3A/DDSPΣ∆ ADC Output DFT[kHz]Amplitude or Integrated Noise [dBFS]0-40-120-160-800 2015105 255kHz, 1Vrms analog inputfilter #2, 24b coefficients fSOUT=46.875kHz1000 point DFT10 averagesEECS 247 Lecture 24: Multi-Rate Filters © 2002 B. Boser 4A/DDSPΣ∆ ADC Output DFTAmplitude or Integrated Noise [dBFS]0-40-120-160-800 2015105 25 [kHz]same as previous slide, except floating point coefficientsà Difference is negligiblestart of decimation filter rolloffEECS 247 Lecture 24: Multi-Rate Filters © 2002 B. Boser 5A/DDSPProduction TestingIt’s obvious that decimation filters obscure many details of modulator analog performance– Most of the shaped quantization noise is filtered away– Was the modulator fabricated correctly? Are there defects in a given chip?– At this stage, you’ve got to consider possible production test modes…EECS 247 Lecture 24: Multi-Rate Filters © 2002 B. Boser 6A/DDSPTest Modes• All Σ∆ ADC designs must provide at least the following test modes:– Output unfiltered 1-bit modulator output samples– Insert test vectors at the decimation filter input• Any mixed-signal IC which includes any ADC must provide for observability of unprocessed ADC output samples– Think of it as fault coverage in the analog domain• Let’s see how our decimation filter obscures a typical modulator manufacturing defect…EECS 247 Lecture 24: Multi-Rate Filters © 2002 B. Boser 7A/DDSPTest Modes• Suppose the modulator is built with an open fault in a metal trace which connects up the switched capacitor implementing the b2capacitor– b2sets one of the quantization noise zeroes– If the b2capacitor is missing, b2=0– In the real world, this defect will occur in 1-10ppm of production units• The next two slides highlight the loop filter defect, and show decimated DFTs with and without the defectEECS 247 Lecture 24: Multi-Rate Filters © 2002 B. Boser 8A/DDSPLoop Filter Defect_k11-z-1++_+b1a2b2a1a3a4a5IN(fromsummer)OUT (to comparator)k2z-11-z-1k3z-11-z-1k4z-11-z-1k5z-11-z-1b2=0 defectEECS 247 Lecture 24: Multi-Rate Filters © 2002 B. Boser 9A/DDSPΣ∆ ADC Output DFTAmplitude (dBFS)0-40-120-160-800 2015105 25 [kHz]5kHz, 1Vrms analog inputfSOUT=46.875kHz1000 point DFT10 averagesb2nominalb2=0 defectEECS 247 Lecture 24: Multi-Rate Filters © 2002 B. Boser 10A/DDSPTest Modes• The small increase in noise above 20kHz would probably be missed in production test– Dynamic range is specified to include only noise from 0-20kHz• Should we ship the defective unit?– Absolutely not– The metal shrapnel pattern associated with the defect is unknown, and it may lead to a catastrophic failure later (reliability problem)• Let’s see if a 1-bit test mode can detect the fault …EECS 247 Lecture 24: Multi-Rate Filters © 2002 B. Boser 11A/DDSPΣ∆ ADC 1-bit Test ModeAmplitude (dBFS)0-40-120-160-800 120906030 150 [kHz]5kHz, 1Vrms analog input30000 point DFT20 averagesb2nominalb2=0 defect10dB shift in noise is easy to detectwithout averagingEECS 247 Lecture 24: Multi-Rate Filters © 2002 B. Boser 12A/DDSPΣ∆ ADC 1-bit Test ModeAmplitude (dBFS)0-40-120-160-800 120906030 150 [kHz]5kHz, 1Vrms analog input30000 point DFT20 averagesb2nominalb2=0 defectmany other loop filter defects leadto visible changes in the highest Qpole in the noise shapeEECS 247 Lecture 24: Multi-Rate Filters © 2002 B. Boser 13A/DDSPTest Modes• Models can analyze whether or not a specific defect is observable with a given test mode– Many defect-observability analyses are required to improve quality levels from ∼100ppm defective to <10ppm defective• These models improve over the production life of a chip and from generation-to-generation– If big customers detect a quality defect, they demand corrective action to improve tests so that units with the same defect won’t be shipped again– Without 1-bit test modes, you’re sunk!EECS 247 Lecture 24: Multi-Rate Filters © 2002 B. Boser 14A/DDSPMultitone Tests• As long as we’re on the subject of testing, let’s examine a fast, effective method to look at the frequency response of a filter or ADC– This method is used extensively in production tests of both analog filters and ADCs– It is not a substitute for classic, fault coverage testing of digital filtersEECS 247 Lecture 24: Multi-Rate Filters © 2002 B. Boser 15A/DDSPMultitone Tests• IC testers can add sinewaves at many different frequencies in the digital domain– The digital sum is sent to a test system DAC which generates the analog input for a device under test– Frequency response at many different input frequencies can be determined with one test • Let’s see how our Σ∆ ADC responds to an input which is a sum of 20, 21, 22, 23, 24.375, 25.375, 26.375, and 27.375kHz sinewavesEECS 247 Lecture 24: Multi-Rate Filters © 2002 B. Boser 16A/DDSPΣ∆ ADC Multitone DFTAmplitude (dBFS)0-40-120-160-800 2015105 25 [kHz]Multitone analog inputfilter #2, 24b coefficients fSOUT=46.875kHz1000 point DFT10 averagesEECS 247 Lecture 24: Multi-Rate Filters © 2002 B. Boser 17A/DDSPΣ∆ ADC Multitone DFTAmplitude (dBFS)0-40-120-160-8015 23211917 25 [kHz]20212223aliased 26.375aliased 25.375aliased 24.37527.375kHz aliasburied by noise!EECS 247 Lecture 24: Multi-Rate Filters © 2002 B. Boser 18A/DDSPMultitone Tests• Note how elegantly the multitone output amplitudes trace the transition band of the decimation filter• Total observation time (1000 ADC output samples) must be long enough to resolve each of the individual frequencies– Hz/bin is the reciprocal of the total observation timeEECS 247 Lecture 24: Multi-Rate Filters © 2002 B. Boser 19A/DDSPMultistage Decimation Filters• Decimation filter #2 can be realized with a accumulator rate of 57MHz, shift register, and coefficient ROM– Absolutely practical in today’s CMOS processes– A multiplier is not
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