EECS 247 Lecture 24 Pipeline ADCs © 2007 H.K. Page 1EE247Lecture 24Pipelined ADCs (continued)– Effect gain stage, sub-DAC non-idealities on overall ADC performance• Digital calibration (continued)• Correction for inter-stage gain nonlinearity– Implementation • Practical circuits• Stage scaling• Combining the bits• Stage implementation–Circuits–Noise budgeting• How many bits per stage?EECS 247 Lecture 24 Pipeline ADCs © 2007 H.K. Page 2Summary Last LectureADC Converters• Techniques to reduce flash ADC complexity (continued)– Interleaved ADCs– Multi-Step ADCs• Two-Step flash• Pipelined ADCs– Effect of sub-ADC non-idealities on overall ADC performance• Error correction by adding redundancy (additional decision levels)EECS 247 Lecture 24 Pipeline ADCs © 2007 H.K. Page 3Summary So Far Pipelined A/D ConvertersVinADC2B1eff2B22B3+-DACADCB2bitsB1bits• Cascade of low resolution stages– Stages operate concurrently- trades latency resolution– Throughput limited by speed of one stage → Fast• Errors and correction– Built-in redundancy compensate for sub-ADC inaccuracies (interstage gain: G=2Bneff, Bneff< Bn)B3bits2B2eff2B3effVrefVrefVrefVrefEECS 247 Lecture 24 Pipeline ADCs © 2007 H.K. Page 4Gain Stage Gain Inaccuracy• Gain error can be compensated in digital domain – "Digital Calibration"• Problem: Need to measure/calibrate digital correction coefficient• Example: Calibrate 1-bit first stage• Objective: Measure G in digital domainEECS 247 Lecture 24 Pipeline ADCs © 2007 H.K. Page 5ADC Model()DACinresVVGV −⋅=12/)1(0)0(refDACDACVDVDV====2VrefGVin⎛⎞⎜⎟⋅−⎝⎠inGV⋅EECS 247 Lecture 24 Pipeline ADCs © 2007 H.K. Page 6Gain Stage Inacurracy Calibration – Step 1Vin= const.+-1-bitDAC1-bitADCD GVres1(1) BackendDback(1)MUX“1“Vref()()storeVVVGDVVGVrefrefinbackrefinres→−⋅=−⋅=2/2/)1()1(1EECS 247 Lecture 24 Pipeline ADCs © 2007 H.K. Page 7Gain Stage Inacurracy Calibration – Step 2Vin= const.+-1-bitDAC1-bitADCD GVres1(2) BackendDback(2)MUX“0“Vref()()storeVVGDVGVrefinbackinres→−⋅=−⋅=00)2()2(1EECS 247 Lecture 24 Pipeline ADCs © 2007 H.K. Page 8Gain Stage Inacurracy Calibration – Evaluate()()GDDVVGDVVVGDbackbackrefinbackrefrefinback⋅=−−−−−−−−−−−−−−−−−−−⋅=−−⋅=2102/)2()1()2()1(• To minimize the effect of backend ADC noise Æ perform measurement several times and take the averageEECS 247 Lecture 24 Pipeline ADCs © 2007 H.K. Page 9Accuracy Bootstrapping• Highest sensitivity to gain errors in front-end stages∏∏−=−−−=−+⎟⎟⎠⎞⎜⎜⎝⎛−++⎟⎟⎠⎞⎜⎜⎝⎛−+⎟⎟⎠⎞⎜⎜⎝⎛−+=11)1()1(21)1(2212111,1...11njdjqnndnnjdjnqddqdqADCinoutGGGGGGGGGVDεεεεΣΣεq1-G1ΣΣΣεq2-G2ΣΣΣεq(n-1)-Gn-1ΣVin,ADCDout1/Gd11/Gd2Vres1Vres2Vres(n-1)Σ1/Gd(n-1)εqnD1D2D(n-1)DnEECS 247 Lecture 24 Pipeline ADCs © 2007 H.K. Page 10"Accuracy Bootstrapping"VinBn bitsStage 3Stage 2Stage 1 Stage k“Sufficiently Accurate“Direction of CalibrationRef: A. N. Karanicolas et al. "A 15-b 1-Msample/s digitally self-calibrated pipeline ADC," IEEE J. Of Solid-State Circuits, pp. 1207-15, Dec. 1993E. G. Soenen et al., "An architecture and an algorithm for fully digital correction of monolithic pipelined ADCs," TCAS II, pp. 143-153, March 1995L. Singer et al., "A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHz," ISSCC 2000, Digest of Tech. Papers., pp. 38-9 (calibration in opposite direction!)EECS 247 Lecture 24 Pipeline ADCs © 2007 H.K. Page 11Pipeline ADCErrors• Non-idealities associated with sub-ADCs, sub-DACs and gain stages Æ error in overall pipeline ADC performance• Need to find means to tolerate/correct errors• Important sources of error– Sub-ADC errors- comparator offset– Gain stage offset– Gain stage error– Sub-DAC errorEECS 247 Lecture 24 Pipeline ADCs © 2007 H.K. Page 12DAC Errors• Can be corrected digitally as well• Same calibration concept as gain errorsÆ Vary DAC codes & measure errors via backend ADCVin+-B1-bitDACDGVres1DbackB1-bitADC+Dout-1/GεDAC+BackendEECS 247 Lecture 24 Pipeline ADCs © 2007 H.K. Page 13DAC Calibration – Step 1• εDAC(0) equivalent to offset - ignore+-B1-bitDACD GVres1DbackB1-bitADC+Dout 1/GεDAC(0) BackendVin= const.MUX“0“+EECS 247 Lecture 24 Pipeline ADCs © 2007 H.K. Page 14DAC Calibration – Step 2...2B1• Stepping through DAC codes 1...2B1-1 yields all incremental correction values• Measurements repeated and averages to account for variance associated with noise+-B1-bitDACDGVres1DbackB1-bitADC+Dout1/GεDAC(1...2B1-1)BackendVin= const.MUX1...2B1-1+Cal. Register-EECS 247 Lecture 24 Pipeline ADCs © 2007 H.K. Page 15Pipeline ADC Example: Calibration Hardware• Above block diagram may seem extensive however, in current fine-line CMOS technologies digital portion of a pipeline ADCs consume insignificant power and area compared to the analog sectionsRef: E. G. Soenen et al., "An architecture and an algorithm for fully digital correction of monolithic pipelined ADCs," TCAS II, pp. 143-153, March 1995EECS 247 Lecture 24 Pipeline ADCs © 2007 H.K. Page 16Pipelined ADC Error Correction/Calibration SummaryVIN1VRES1DACD1-a3V3+23ADC+VOS++εADC+εDACεgainEither sufficient component matching or digital calibrationεDAC?Inter-stage amplifier non-linearityDigital adjustmentεgainRedundancy either same stage or next stageεADC, VosCorrection/CalibrationErrorEECS 247 Lecture 24 Pipeline ADCs © 2007 H.K. Page 17Inter-stage Gain NonlinearityRef: B. Murmann and B. E. Boser, "A 12-b, 75MS/s Pipelined ADC using Open-Loop Residue Amplification," ISSCC Dig. Techn. Papers, pp. 328-329, 2003• Invert gain stage non-linear polynomial• Express error as function of VRES1• Push error into digital domain through backendEECS 247 Lecture 24
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