EE247 Lecture 24 Pipelined ADCs continued Effect gain stage sub DAC non idealities on overall ADC performance Digital calibration continued Correction for inter stage gain nonlinearity Implementation Practical circuits Stage scaling Combining the bits Stage implementation Circuits Noise budgeting How many bits per stage EECS 247 Lecture 24 Pipeline ADCs 2007 H K Page 1 Summary Last Lecture ADC Converters Techniques to reduce flash ADC complexity continued Interleaved ADCs Multi Step ADCs Two Step flash Pipelined ADCs Effect of sub ADC non idealities on overall ADC performance Error correction by adding redundancy additional decision levels EECS 247 Lecture 24 Pipeline ADCs 2007 H K Page 2 Summary So Far Pipelined A D Converters Vref Vref Vin B1 bits 2B1eff Vref B2 22B2eff B2 bits DAC ADC B3 bits Vref ADC B3 2 2B3eff Cascade of low resolution stages Stages operate concurrently trades latency resolution Throughput limited by speed of one stage Fast Errors and correction Built in redundancy compensate for sub ADC inaccuracies interstage gain G 2Bneff Bneff Bn EECS 247 Lecture 24 Pipeline ADCs 2007 H K Page 3 Gain Stage Gain Inaccuracy Gain error can be compensated in digital domain Digital Calibration Problem Need to measure calibrate digital correction coefficient Example Calibrate 1 bit first stage Objective Measure G in digital domain EECS 247 Lecture 24 Pipeline ADCs 2007 H K Page 4 ADC Model Vref G Vin 2 Vres1 G Vin VDAC VDAC D 0 0 G Vin VDAC D 1 Vref 2 EECS 247 Lecture 24 Pipeline ADCs 2007 H K Page 5 Gain Stage Inacurracy Calibration Step 1 Vref Vin const 1 bit ADC G Backend Dback 1 1 bit DAC M U X D Vres1 1 1 Vres1 G Vin Vref 2 1 Dback EECS 247 Lecture 24 1 G V in Vref 2 Vref Pipeline ADCs store 2007 H K Page 6 Gain Stage Inacurracy Calibration Step 2 Vin const 1 bit ADC Backend Dback 2 1 bit DAC M U X D Vres1 2 G Vref 0 Vres1 2 Dback G Vin 0 2 EECS 247 Lecture 24 G Vin 0 store Vref Pipeline ADCs 2007 H K Page 7 Gain Stage Inacurracy Calibration Evaluate Dback Dback 1 2 G G V in Vref 2 Vref Vin 0 Vref 1 1 2 Dback Dback G 2 To minimize the effect of backend ADC noise perform measurement several times and take the average EECS 247 Lecture 24 Pipeline ADCs 2007 H K Page 8 Accuracy Bootstrapping Vin ADC Vres1 G 1 q1 Dout D1 Vres2 G 2 q2 1 Gd1 D2 Vres n 1 G n 1 q n 1 1 Gd2 G q2 G 1 2 n q2 n 1 Dout Vin ADC q1 1 1 Gd 1 Gd 1 Gd 2 Gdj j 1 qn D n 1 Dn 1 Gd n 1 G 1 n 1 qn n 1 G d n 1 Gdj j 1 Highest sensitivity to gain errors in front end stages EECS 247 Lecture 24 Pipeline ADCs 2007 H K Page 9 Accuracy Bootstrapping Direction of Calibration Vin Stage 1 Stage 2 Stage 3 Sufficiently Accurate Stage k Bn bits Ref A N Karanicolas et al A 15 b 1 Msample s digitally self calibrated pipeline ADC IEEE J Of Solid State Circuits pp 1207 15 Dec 1993 E G Soenen et al An architecture and an algorithm for fully digital correction of monolithic pipelined ADCs TCAS II pp 143 153 March 1995 L Singer et al A 12 b 65 MSample s CMOS ADC with 82 dB SFDR at 120 MHz ISSCC 2000 Digest of Tech Papers pp 38 9 calibration in opposite direction EECS 247 Lecture 24 Pipeline ADCs 2007 H K Page 10 Pipeline ADC Errors Non idealities associated with sub ADCs sub DACs and gain stages error in overall pipeline ADC performance Need to find means to tolerate correct errors Important sources of error Sub ADC errors comparator offset Gain stage offset Gain stage error Sub DAC error EECS 247 Lecture 24 Pipeline ADCs 2007 H K Page 11 DAC Errors Vin B1 bit ADC B1 bit DAC Vres1 Backend DAC D Dout G 1 G Dback Can be corrected digitally as well Same calibration concept as gain errors Vary DAC codes measure errors via backend ADC EECS 247 Lecture 24 Pipeline ADCs 2007 H K Page 12 DAC Calibration Step 1 Vin const B1 bit ADC B1 bit DAC M U X D G Vres1 Backend DAC 0 0 Dout Dback 1 G DAC 0 equivalent to offset ignore EECS 247 Lecture 24 Pipeline ADCs 2007 H K Page 13 DAC Calibration Step 2 2B1 Vin const B1 bit ADC D M U X B1 bit DAC 1 2B1 1 Dout G Vres1 Backend DAC 1 2B1 1 Cal Register 1 G Dback Stepping through DAC codes 1 2B1 1 yields all incremental correction values Measurements repeated and averages to account for variance associated with noise EECS 247 Lecture 24 Pipeline ADCs 2007 H K Page 14 Pipeline ADC Example Calibration Hardware Above block diagram may seem extensive however in current fine line CMOS technologies digital portion of a pipeline ADCs consume insignificant power and area compared to the analog sections Ref E G Soenen et al An architecture and an algorithm for fully digital correction of monolithic pipelined ADCs TCAS II pp 143 153 March 1995 EECS 247 Lecture 24 Pipeline ADCs 2007 H K Page 15 Pipelined ADC Error Correction Calibration Summary VOS VIN1 ADC ADC 23 VRES1 gain DAC a3V3 DAC D1 Error Correction Calibration ADC Vos Redundancy either same stage or next stage gain Digital adjustment DAC Either sufficient component matching or digital calibration Inter stage amplifier non linearity EECS 247 Lecture 24 Pipeline ADCs 2007 H K Page 16 Inter stage Gain Nonlinearity Invert gain stage non linear polynomial Express error as function of VRES1 Push error into digital domain through backend Ref B Murmann and B E Boser A 12 b 75MS s Pipelined ADC using Open Loop Residue Amplification ISSCC Dig Techn Papers pp 328 329 2003 EECS 247 Lecture 24 Pipeline ADCs 2007 H K Page 17 Inter stage Gain Nonlinearity a3VX3 VX 23 gain VRES1 Backend DB a p2 3 3 3 2 gain DB corr DB p2 DB p2 p2DB3 3p22DB5 12p23DB7 Pre computed table look up p2 continuously estimated updated account for temp other variations Ref B Murmann and B E Boser A 12 b 75MS s Pipelined ADC using Open Loop Residue Amplification ISSCC Dig Techn Papers pp 328 329 2003 EECS 247 Lecture 24 Pipeline ADCs 2007 H K Page 18 Inter stage Gain Nonlinearity Compensation Proof of Concept Evaluation Prototype Re used 14 bit ADC in 0 35 m from Analog Devices Kelly ISSCC 2001 Modified only 1st stage with 3 beff open loop amplifier built with simple diff pair resistive load instead of the conventional feedback around high gain amp Conventional 9 beff backend 2 bit redundancy in 1st stage Real time post processor off chip FPGA Ref B Murmann and B E Boser A 12 b 75MS s Pipelined ADC using Open Loop Residue Amplification ISSCC Dig Techn Papers pp 328 329 2003 EECS 247 …
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