EECS 247 Lecture 20: Data Converters © 2006 H.K. Page 1EE247Lecture 20ADC Converters– Sampling (continued)• Track & hold circuits• T/H combined with summing/difference function• T/H circuit incorporating gain & offset cancellation–Electro-Static Discharge (ESD) protection– ADC architectures (today)• Serial- slope type• Successive approximation•FlashEECS 247 Lecture 20: Data Converters © 2006 H.K. Page 2Summary Last LectureADC Converters• Sampling (continued)– Clock boosters (continued)– Sampling switch charge injection & clock feedthrough• Complementary switch• Use of dummy device• Bottom-plate switching– Track & hold circuitsEECS 247 Lecture 20: Data Converters © 2006 H.K. Page 3Differential Flip-Around T/HIssues: Input Common-Mode Range• ΔVin-cm=Vout_com-Vsig_com Æ Amplifier needs to have large input common-mode complianceEECS 247 Lecture 20: Data Converters © 2006 H.K. Page 4Input Common-Mode CancellationRef: R. Yen, et al. “A MOS Switched-Capacitor Instrumentation Amplifier,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-17, NO. 6,, DECEMBER 1982 1008• Note: Shorting switch M3 addedEECS 247 Lecture 20: Data Converters © 2006 H.K. Page 5Input Common-Mode CancellationTrack mode (φ high)VC1=VI1, VC2=VI2Vo1=Vo2=0Hold mode (φ low)Vo1+Vo2=0Vo1-Vo2= -(VI1-VI2)(C1/(C1+C3))Æ Input common-mode level removedEECS 247 Lecture 20: Data Converters © 2006 H.K. Page 6T/H + Charge Redistribution AmplifierTrack mode: (S1, S3 Æon S2Æ off)VC1=Vos–VIN, VC2=0Vo=VosEECS 247 Lecture 20: Data Converters © 2006 H.K. Page 7T/H + Charge Redistribution AmplifierHold ModeHold/amplify mode (S1, S3 Æoff S2Æ on)Æ Offset NOT cancelled, but not amplifiedÆ Input-referred offset =(C2/C1) x VOS, & often C2<C1212EECS 247 Lecture 20: Data Converters © 2006 H.K. Page 8T/H & Input Difference AmplifierSample mode (S1, S3 Æon S2Æ off)VC1=Vos–VI1, VC2=0Vo=VosEECS 247 Lecture 20: Data Converters © 2006 H.K. Page 9Input Difference AmplifierCont‘dSubtract/Amplify mode (S1, S3 Æoff S2Æ on)During previous phase:VC1=Vos–VI1, VC2=0Vo=Vos1ÆOffset NOT cancelled, but not amplifiedÆInput-referred offset =(C2/C1)xVOS, & C2<C1EECS 247 Lecture 20: Data Converters © 2006 H.K. Page 10T/H & Summing AmplifierEECS 247 Lecture 20: Data Converters © 2006 H.K. Page 11T/H & Summing AmplifierCont‘dSample mode (S1, S3, S5Æon S2, S4Æ off)VC1=Vos–VI1, VC2=Vos-VI3, VC3=0Vo=VosEECS 247 Lecture 20: Data Converters © 2006 H.K. Page 12T/H & Summing AmplifierCont‘dAmplify mode (S1, S3, S5Æoff, S2, S4Æ on)3EECS 247 Lecture 20: Data Converters © 2006 H.K. Page 13Differential T/H Combined with Gain StageRef: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987Employs the previously discussed technique to eliminate the problem associated with high common-mode voltage excursion at the input of the opampEECS 247 Lecture 20: Data Converters © 2006 H.K. Page 14Ref: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987Differential T/H Combined with Gain Stageφ1 Æ HighEECS 247 Lecture 20: Data Converters © 2006 H.K. Page 15Ref: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987• Gain=4C/C=4• Input voltage common-mode level removed Æopamp can have low input common-mode compliance• Amplifier offset NOT removedDifferential T/H Combined with Gain StageEECS 247 Lecture 20: Data Converters © 2006 H.K. Page 16Ref: H. Ohara, et al., "A CMOS programmable self-calibrating 13-bit eight-channel data acquisition peripheral," IEEE Journal of Solid-State Circuits, vol. 22, pp. 930 - 938, December 1987. • Operation during offset cancellation phase shown• Auxilary inputs added with Amain/Aaux.=10• During offset cancellation phase:•Aux. amp configured in unity-gain mode: Vout=Vosmain Æ offset stored on CAZ& canceledDifferential T/H Including Offset CancellationEECS 247 Lecture 20: Data Converters © 2006 H.K. Page 17Differential T/H Including Offset CancellationOperational AmplifierRef: H. Ohara, et al., "A CMOS programmable self-calibrating 13-bit eight-channel data acquisition peripheral," IEEE Journal of Solid-State Circuits, vol. 22, pp. 930 - 938, December 1987. • Operational amplifier Ædual input folded-cascode opamp• M3,4 auxiliary input, M1,2 main input• To achieve 1/10 gain ratio WM3, 4=1/10x WM1,2& current sources are scaled by 1/10• M5,6,7 Æ common-mode control • Output stage Æ dual cascode Æ high DC gainVout=gm1,2roVin1+ gm3,4roVin2EECS 247 Lecture 20: Data Converters © 2006 H.K. Page 18• During offset cancellation phase AZ and S1 closed Æ main amplifier offset amplified by gm1/gm2& stored on CAZ• Auxiliary amp chosen to have lower gain so that: Aux. amp charge injection associated with opening of switch AZ Æ reduced by Aaux/Amain=1/10Insignificant increase in power dissipation resulting from addition of aux. inputs• Requires an extra auto-zero clock phaseDifferential T/H Including Offset Cancellation PhaseVoffset+-(VINAZ+-VINAZ-)= -gm1,2/gm3,4VoffsetEECS 247 Lecture 20: Data Converters © 2006 H.K. Page 19Differential Flip-Around T/HChoice of Sampling Switch SizeRef: K. Vleugels et al, “A 2.5-V Sigma–Delta Modulator for Broadband Communications Applications “ IEEE JSSC, VOL. 36, NO. 12, DECEMBER 2001, pp. 1887• THD simulated w/o sampling switch boosted clock Æ -45dB• THD simulated with sampling switch boosted clock (see figure)EECS 247 Lecture 20: Data Converters © 2006 H.K. Page 20Track & HoldAperture Time ErrorTimeVVinVOM1VCLKVinVin +VTHVCLKTransition from track to hold:Occurs when device turns fully offÆ VCLK=Vin+VTHSharp fall-time wrt signal changeÆ no aperture errorCsEECS 247 Lecture 20: Data Converters © 2006 H.K. Page 21Track & HoldAperture Time ErrorTimeVSlow clock Æ aperture errorVin=A sin(2π fin t)ε= fin xAx tfall /VCLKSDR= - 20logε -4 [dB] (see Ref.)Example: Nyquist rate 10-bit ADC & A=VCLK /4ÆSQNR=62dB for SDR due to aperture error < quant errorÆ tfall< 2x10-3/fin Æ Worst case: fin= fs/2Æ tfall < 4x10-3/fs Æe.g. fs=100MHz tfall<40psecVinVin +VTHVCLKRef: P. J. Lim and B. A. Wooley, "A high-speed sample-and-hold technique using a Miller hold capacitance," IEEE Journal of Solid-State Circuits, vol. 26, pp. 643 - 651,
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