EE247 Lecture 20 ADC Converters Sampling continued Track hold circuits T H combined with summing difference function T H circuit incorporating gain offset cancellation Electro Static Discharge ESD protection ADC architectures today Serial slope type Successive approximation Flash EECS 247 Lecture 20 Data Converters 2006 H K Page 1 Summary Last Lecture ADC Converters Sampling continued Clock boosters continued Sampling switch charge injection clock feedthrough Complementary switch Use of dummy device Bottom plate switching Track hold circuits EECS 247 Lecture 20 Data Converters 2006 H K Page 2 Differential Flip Around T H Issues Input Common Mode Range Vin cm Vout com Vsig com Amplifier needs to have large input common mode compliance EECS 247 Lecture 20 Data Converters 2006 H K Page 3 Input Common Mode Cancellation Note Shorting switch M3 added Ref R Yen et al A MOS Switched Capacitor Instrumentation Amplifier IEEE JOURNAL OF SOLID STATE CIRCUITS VOL SC 17 NO 6 DECEMBER 1982 1008 EECS 247 Lecture 20 Data Converters 2006 H K Page 4 Input Common Mode Cancellation Track mode high VC1 VI1 VC2 VI2 Vo1 Vo2 0 Hold mode low Vo1 Vo2 0 Vo1 Vo2 VI1 VI2 C1 C1 C3 Input common mode level removed EECS 247 Lecture 20 Data Converters 2006 H K Page 5 T H Charge Redistribution Amplifier Track mode S1 S3 on S2 off VC1 Vos VIN VC2 0 Vo Vos EECS 247 Lecture 20 Data Converters 2006 H K Page 6 T H Charge Redistribution Amplifier Hold Mode 22 1 Hold amplify mode S1 S3 off S2 on Offset NOT cancelled but not amplified Input referred offset C2 C1 x VOS often C2 C1 EECS 247 Lecture 20 Data Converters 2006 H K Page 7 T H Input Difference Amplifier Sample mode S1 S3 on S2 off VC1 Vos VI1 VC2 0 Vo Vos EECS 247 Lecture 20 Data Converters 2006 H K Page 8 Input Difference Amplifier Cont d Subtract Amplify mode S1 S3 off S2 on During previous phase VC1 Vos VI1 VC2 0 Vo Vos 1 Offset NOT cancelled but not amplified Input referred offset C2 C1 xVOS C2 C1 EECS 247 Lecture 20 Data Converters 2006 H K Page 9 T H Summing Amplifier EECS 247 Lecture 20 Data Converters 2006 H K Page 10 T H Summing Amplifier Cont d Sample mode S1 S3 S5 on S2 S4 off VC1 Vos VI1 VC2 Vos VI3 VC3 0 Vo Vos EECS 247 Lecture 20 Data Converters 2006 H K Page 11 T H Summing Amplifier Cont d Amplify mode S1 S3 S5 off S2 S4 on 3 EECS 247 Lecture 20 Data Converters 2006 H K Page 12 Differential T H Combined with Gain Stage Employs the previously discussed technique to eliminate the problem associated with high common mode voltage excursion at the input of the opamp Ref S H Lewis et al A Pipelined 5 Msample s 9 bit Analog to Digital Converter IEEE JSSC VOL SC 22 NO 6 DECEMBER 1987 EECS 247 Lecture 20 Data Converters 2006 H K Page 13 Differential T H Combined with Gain Stage 1 High Ref S H Lewis et al A Pipelined 5 Msample s 9 bit Analog to Digital Converter IEEE JSSC VOL SC 22 NO 6 DECEMBER 1987 EECS 247 Lecture 20 Data Converters 2006 H K Page 14 Differential T H Combined with Gain Stage Gain 4C C 4 Input voltage common mode level removed opamp can have low input common mode compliance Amplifier offset NOT removed Ref S H Lewis et al A Pipelined 5 Msample s 9 bit Analog to Digital Converter IEEE JSSC VOL SC 22 NO 6 DECEMBER 1987 EECS 247 Lecture 20 Data Converters 2006 H K Page 15 Differential T H Including Offset Cancellation Operation during offset cancellation phase shown Auxilary inputs added with Amain Aaux 10 During offset cancellation phase Aux amp configured in unity gain mode Vout Vosmain offset stored on CAZ canceled Ref H Ohara et al A CMOS programmable self calibrating 13 bit eight channel data acquisition peripheral IEEE Journal of Solid State Circuits vol 22 pp 930 938 December 1987 EECS 247 Lecture 20 Data Converters 2006 H K Page 16 Differential T H Including Offset Cancellation Operational Amplifier Operational amplifier dual input folded cascode opamp M3 4 auxiliary input M1 2 main input To achieve 1 10 gain ratio WM3 4 1 10x WM1 2 current sources are scaled by 1 10 M5 6 7 common mode control Output stage dual cascode high DC gain Vout gm1 2roVin1 gm3 4roVin2 Ref H Ohara et al A CMOS programmable self calibrating 13 bit eight channel data acquisition peripheral IEEE Journal of Solid State Circuits vol 22 pp 930 938 December 1987 EECS 247 Lecture 20 Data Converters 2006 H K Page 17 Differential T H Including Offset Cancellation Phase VINAZ VINAZ gm1 2 gm3 4Voffset Voffset During offset cancellation phase AZ and S1 closed main amplifier offset amplified by gm1 gm2 stored on CAZ Auxiliary amp chosen to have lower gain so that Aux amp charge injection associated with opening of switch AZ reduced by Aaux Amain 1 10 Insignificant increase in power dissipation resulting from addition of aux inputs Requires an extra auto zero clock phase EECS 247 Lecture 20 Data Converters 2006 H K Page 18 Differential Flip Around T H Choice of Sampling Switch Size THD simulated w o sampling switch boosted clock 45dB THD simulated with sampling switch boosted clock see figure Ref K Vleugels et al A 2 5 V Sigma Delta Modulator for Broadband Communications Applications IEEE JSSC VOL 36 NO 12 DECEMBER 2001 pp 1887 EECS 247 Lecture 20 Data Converters 2006 H K Page 19 Track Hold Aperture Time Error V VCLK VCLK Vin VTH Vin Vin VO M1 Cs Transition from track to hold Occurs when device turns fully off VCLK Vin VTH Time EECS 247 Lecture 20 Data Converters Sharp fall time wrt signal change no aperture error 2006 H K Page 20 V VCLK Track Hold Aperture Time Error Vin VTH Vin Time Slow clock aperture error Vin A sin 2 fin t fin xAx tfall VCLK SDR 20log 4 dB see Ref Example Nyquist rate 10 bit ADC A VCLK 4 SQNR 62dB for SDR due to aperture error quant error tfall 2x10 3 fin Worst case fin fs 2 tfall 4x10 3 fs e g fs 100MHz tfall 40psec Ref P J Lim and B A Wooley A high speed sample and hold technique using a Miller hold capacitance IEEE Journal of Solid State Circuits vol 26 pp 643 651 April 1991 EECS 247 Lecture 20 Data Converters 2006 H K Page 21 Track Hold Aperture Time Error Aperture error analysis applies to simple sampling network Bottom plate sampling minimizes aperture error Boosted clock reduces aperture error In general Clock fall rise trade off between switch charge injection versus aperture error Ref P J Lim and B A Wooley A high speed sample and hold technique using a Miller hold capacitance IEEE Journal of Solid State Circuits vol 26 pp 643 651 April 1991 EECS 247 Lecture 20 Data Converters 2006 H K Page 22 ESD Protection ADC Architectures …
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