EE247 Lecture 25 Pipelined ADCs continued How many bits per stage Algorithmic ADCs utilizing pipeline structure Advanced background calibration techniques Oversampled ADCs Why oversampling Pulse count modulation Sigma delta modulation 1 Bit quantization Quantization error noise spectrum SQNR analysis Limit cycle oscillations EECS 247 Lecture 25 Pipeline Oversampled ADCs 2007 H K Page 1 Summary Last Lecture Pipelined ADCs continued Effect gain stage sub DAC non idealities on overall ADC performance Digital calibration continued Correction for inter stage gain nonlinearity Implementation Practical circuits Combining the digital bits Stage implementation Circuits Noise budgeting EECS 247 Lecture 25 Pipeline Oversampled ADCs 2007 H K Page 2 How Many Bits Per Stage Many possible architectures E g B1eff 3 B2eff 1 vs B1eff 1 B2eff 1 B3eff 1 Complex optimization problem fortunately optimum tends to be shallow Qualitative answer Maximum speed for given technology Use small resolution per stage large feedback factor Maximum power efficiency for fixed low speed Try higher resolution stages Can help alleviate matching noise requirements in stages following the 1st stage Ref Singer VLSI 96 Yang JSSC 12 01 EECS 247 Lecture 25 Pipeline Oversampled ADCs 2007 H K Page 3 14 12 Bit State of the Art Implementations Yang Loloee JSSC 12 2001 0 35 3V ESSIRC 2002 0 18 3V 14 12 Architecture 3 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 1 2 SNR SFDR 73dB 88dB 66dB 75dB Speed 75MS s 80MS s Power 340mW 260mW Reference Bits EECS 247 Lecture 25 Pipeline Oversampled ADCs 2007 H K Page 4 10 8 Bit State of the Art Implementations Yoshioko et al ISSCC 2005 0 18 1 8V Kim et al ISSCC 2005 0 18 1 8V 10 8 Architecture 1 5bit stage 2 8 2 8 4 SNR SFDR 55dB 66dB 48dB 56dB Speed 125MS s 200MS s Power 40mW 30mW Reference Bits EECS 247 Lecture 25 Pipeline Oversampled ADCs 2007 H K Page 5 Algorithmic ADC Digital Output start of conversion VIN T H Shift Register Correction Logic Residue sub ADC 1 6 Bit DAC 2B Essentially same as pipeline but a single stage is reused for all partial conversions For overall Boverall bits need Boverall Bstage clock cycles per conversion Small area slow EECS 247 Lecture 25 Pipeline Oversampled ADCs 2007 H K Page 6 Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog to Digital Converters Slow but accurate ADC operates in parallel with pipelined main ADC Slow ADC samples input signal at a lower sampling rate fs n Difference between corresponding samples for two ADCs e used to correct fast ADC digital output via an adaptive digital filter ADF based on minimizing the Least Mean Squared error Ref Y Chiu et al Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog to Digital Converters IEEE TRANS CAS VOL 51 NO 1 JANUARY 2004 EECS 247 Lecture 25 Pipeline Oversampled ADCs 2007 H K Page 7 Example A 12 bit 20 MS s pipelined analog to digital converter with nested digital background calibration Pipelined ADC operates at 20Ms s has 1 5bit stage Slow ADC Algorithmic type operating at 20Ms 32 625ks s Digital correction accounts for bit redundancy Digital error estimator minimizes the mean squared error Ref X Wang P J Hurst S H Lewis A 12 bit 20 Msample s pipelined analog to digital converter with nested digital background calibration IEEE JSSC vol 39 pp 1799 1808 Nov 2004 EECS 247 Lecture 25 Pipeline Oversampled ADCs 2007 H K Page 8 Algorithmic ADC Used for Calibration of Pipelined ADC continued from previous page Uses replica of pipelined ADC stage Requires extra SHA in front to hold residue Undergoes a calibration cycle periodically prior to being used to calibrate pipelined ADC Ref X Wang P J Hurst S H Lewis A 12 bit 20 MS s pipelined analog to digital converter with nested digital background calibration IEEE JSSC vol 39 pp 1799 1808 Nov 2004 EECS 247 Lecture 25 Pipeline Oversampled ADCs 2007 H K Page 9 12 bit 20 MS s Pipelined ADC with Digital Background Calibration Sampling capacitors scaled Input SHA 6pF Pipelined ADC 2pF 0 9 0 4 0 2 0 1 0 1 Algorithmic ADC 0 2pF Chip area 13 2mm2 Area of Algorithmic ADC 20 Does not include digital calibration circuitry estimated 1 7mm2 Ref X Wang P J Hurst S H Lewis A 12 bit 20 MS s pipelined analog to digital converter with nested digital background calibration IEEE JSSC vol 39 pp 1799 1808 Nov 2004 EECS 247 Lecture 25 Pipeline Oversampled ADCs 2007 H K Page 10 Measurement Results 12 bit 20 MS s Pipelined ADC with Digital Background Calibration Without Calibration INL 4 2LSB With Calibration INL 0 5LSB Ref X Wang P J Hurst S H Lewis A 12 bit 20 MS s pipelined analog to digital converter with nested digital background calibration IEEE JSSC vol 39 pp 1799 1808 Nov 2004 EECS 247 Lecture 25 Pipeline Oversampled ADCs 2007 H K Page 11 Measurement Results 12 bit 20 MS s Pipelined ADC with Digital Background Calibration Nyquist rate Ref X Wang P J Hurst S H Lewis A 12 bit 20 MS s pipelined analog to digital converter with nested digital background calibration IEEE JSSC vol 39 pp 1799 1808 Nov 2004 EECS 247 Lecture 25 Pipeline Oversampled ADCs 2007 H K Page 12 Measurement Results 12 bit 20 MS s Pipelined ADC with Digital Background Calibration Does not include digital calibration circuitry estimated 1 7mm2 Alg ADC SNDR dominated by noise Ref X Wang P J Hurst S H Lewis A 12 bit 20 MS s pipelined analog to digital converter with nested digital background calibration IEEE JSSC vol 39 pp 1799 1808 Nov 2004 EECS 247 Lecture 25 Pipeline Oversampled ADCs 2007 H K Page 13 Oversampled ADCs EECS 247 Lecture 25 Pipeline Oversampled ADCs 2007 H K Page 14 Analog to Digital Converters Two categories Nyquist rate ADCs fsigmax 0 5xfsampling Maximum achievable signal bandwidth higher compared to oversampled type Resolution limited to max 12 14bits Oversampled ADCs fsigmax 0 5xfsampling Maximum possible signal bandwidth lower compared to nyquist Maximum achievable resolution high 18 to 20bits EECS 247 Lecture 25 Pipeline Oversampled ADCs 2007 H K Page 15 The Case for Oversampling Nyquist sampling fs Signal narrow transition B Freq AA Filter fs 2B Sampler Nyquist ADC Oversampling fs fN Signal B Freq DSP wide transition fs M fN AA Filter Sampler Oversampled ADC DSP Nyquist rate fN 2B Oversampling rate M fs fN 1 EECS 247 Lecture 25 Pipeline Oversampled ADCs 2007 H K Page 16 Nyquist v s Oversampled Converters Antialiasing X f Input Signal frequency fB Nyquist Sampling fB fs fS 2fB Anti aliasing Filter 2fs frequency Oversampling fB EECS 247 Lecture 25 fS
View Full Document
Unlocking...