Notes on the Class Project ENOB 6bit for the case Input test signal a 10MHz full scale sinusoidal signal No non idealities such as comparator offset added Note that Transient analysis in Spectre or HSpice does not include device noise Device models do not address charge injection for switches Results obtained from transient analysis FFT will indicate performance better than measured data from actual silicon EECS 247 Lecture 24 Oversampled ADCs 2009 Page 1 EE247 Lecture 24 Oversampled ADCs continued 2nd order modulator Practical implementation Effect of various building block nonidealities on the performance Integrator maximum signal handling capability Integrator finite DC gain Comparator hysteresis minimum signal handling capability Integrator non linearity Effect of KT C noise Finite opamp bandwidth Opamp slew limited settling Implementation example Higher order modulators Cascaded modulators multi stage Single loop single quantizer modulators with multi order filtering in the forward path EECS 247 Lecture 24 Oversampled ADCs 2009 Page 2 Implementation Practical Design Considerations Internal node scaling clipping Effect of finite opamp gain linearity KT C noise Opamp noise Finite opamp bandwidth Opamp slew limited settling Effect of comparator nonidealities Power dissipation considerations EECS 247 Lecture 24 Oversampled ADCs 2009 Page 3 Switched Capacitor Implementation 2nd Order Nodes Scaled for Maximum Dynamic Range Modification gain of in front of integrators reduce optimize required signal range at the integrator outputs 1 7x input full scale Note Non idealities associated with 2nd integrator and quantizer when referred to the input is attenuated by 1st integrator high gain The only building block requiring low noise and high accuracy is the 1st integrator Ref B E Boser and B A Wooley The Design of Sigma Delta Modulation A D Converters IEEE J Solid State Circuits vol 23 no 6 pp 1298 1308 Dec 1988 EECS 247 Lecture 24 Oversampled ADCs 2009 Page 4 2nd Order Modulator Example Switched Capacitor Implementation Dout VIN Fully differential front end Two bottom plate integrators 1 bit DAC is made of switches and Vrefs EECS 247 Lecture 24 Oversampled ADCs 2009 Page 5 2nd Order Modulator Switched Capacitor Implementation The loss in front of each integrator implemented by choice of C2 2C1 EECS 247 Lecture 24 f0intg fs 4 Oversampled ADCs 2009 Page 6 Design Phase Simulations Design of oversampled ADCs requires simulation of extremely long data traces due to the oversampled nature of the system SPICE type simulators Normally used to test for gross circuit errors only Too slow for detailed performance verification Typically behavioral modeling is used in MATLAB like environments Circuit non idealities either computed or found by using SPICE at subcircuit level Non idealities introduced in the behavioral model one by one first to fully understand the effect of each individually Next step is to add as many of the non idealities simultaneously as possible to verify whether there are interaction among non idealities EECS 247 Lecture 24 Oversampled ADCs 2009 Page 7 Testing of AFE Typically in the design phase provisions are made to test the AFE separate from Decimator Output of the AFE 0 1 is acquired by a data acquisition board or logic analyzer Matlab like program is used to analyze data e g perform filtering measure SNR SNDR During pre silicon design phase output of AFE is filtered in software Matlab used to measure SNR SNDR fs Filtered Sinwave EECS 247 Lecture 24 AFE Data Acq Oversampled ADCs PC Matlab 2009 Page 8 Example Testing ADC Note The Nyquist ADC tests such as INL and DNL test do not apply to modulator type ADCS 2nd order M 256 a tic aly n A n sio es r xp lE re su a Me d testing is performed via SNDR as a function of input signal level EECS 247 Lecture 24 Overload Point Oversampled ADCs 2009 Page 9 2nd Order Effect of 1st Integrator Maximum Signal Handling Capability on SNR M 256 Behavioral model Non idealities tested one by one 1st integrator maximum signal handling 1 4 1 5 1 6 and 1 7X Effect of 1st Integrator maximum signal handling capability on converter SNR No SNR loss for max sig handling 1 7 Ref B E Boser et al The Design of Sigma Delta Modulation A D Converters JSSC Dec 1988 EECS 247 Lecture 24 Oversampled ADCs 2009 Page 10 2nd Order Effect of 2nd Integrator Maximum Signal Handling Capability on SNR 2nd integrator maximum signal handling 0 75 1 1 25 1 5 and 1 7X Effect of 2nd Integrator maximum signal handling capability on SNR SNR loss for max sig handling 1 7 Ref B E Boser et al The Design of Sigma Delta Modulation A D Converters JSSC Dec 1988 EECS 247 Lecture 24 Oversampled ADCs 2009 Page 11 2nd Order Effect of Integrator Finite DC Gain Integrator 1 CI 2 Cs a Vo Vi a opamp gain at DC EECS 247 Lecture 24 Cs z 1 CI 1 z 1 1 a z Cs 1 a Cs CI H z Finit DC Gain CI 1 a 1 z 1 Cs 1 a CI H DC a H z ideal Oversampled ADCs 2009 Page 12 1nd Order Effect of Integrator Finite DC Gain Analysis l o g H s Ideal Integ a infinite eQ DOUT a H 0 0 P1 a Integrator magnitude response Dout 1 eQ 1 H Note Quantization transfer function wrt output has integrator in the feedback path EECS 247 Lecture 24 D C for ide al inte g D o ut 0 eQ D ou t 1 D C for real integ eQ a Oversampled ADCs 2009 Page 13 1st 2nd Order Effect of Integrator Finite DC Gain Max signal level a f0 a Low integrator DC gain Increase in total in band quantization noise Can be shown If a M oversampling ratio Insignificant degradation in SNR Normally DC gain designed to be M in order to suppress nonlinearities EECS 247 Lecture 24 Oversampled ADCs 2009 Page 14 2nd Order Effect of Integrator Finite DC Gain M a Example a 2M 0 4dB degradation in SNR a M 1 4dB degradation in SNR Ref B E Boser et al The Design of Sigma Delta Modulation A D Converters JSSC Dec 1988 EECS 247 Lecture 24 Oversampled ADCs 2009 Page 15 2nd Order Effect of Comparator Non Idealities on Performance 1 bit A D Single comparator Speed must be adequate for the operating sampling rate Input referred offset feedback loop high DC intg gain suppresses the effect performance quite insensitive to comparator offset Input referred comparator noise same as offset Hysteresis Minimum overdrive required to change the output EECS 247 Lecture 24 Oversampled ADCs 2009 Page 16 2nd Order Comparator Hysteresis Hysteresis Minimum overdrive required to change the output EECS 247 Lecture 24 Oversampled ADCs 2009 Page 17 2nd Order Comparator Hysteresis Hysteresis Comparator
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