EECS 247- Lecture 24 Oversampled ADCs © 2009 Page 1Notes on the Class Project- ENOB=6bit for the case:• Input test signal a 10MHz full-scale sinusoidal signal• No non-idealities such as comparator offset added• Note that:– Transient analysis in Spectre or HSpice does not include device noise– Device models do not address charge injection for switchesÆResults obtained from transient analysis + FFT will indicate performance better than measured data from actual siliconEECS 247- Lecture 24 Oversampled ADCs © 2009 Page 2EE247Lecture 24Oversampled ADCs (continued)–2ndorder ΣΔ modulator• Practical implementation– Effect of various building block nonidealities on the ΣΔperformance• Integrator maximum signal handling capability • Integrator finite DC gain • Comparator hysteresis (minimum signal handling capability)• Integrator non-linearity • Effect of KT/C noise• Finite opamp bandwidth• Opamp slew limited settling– Implementation example–Higher order ΣΔ modulators• Cascaded modulators (multi-stage)• Single-loop single-quantizer modulators with multi-order filtering in the forward pathEECS 247- Lecture 24 Oversampled ADCs © 2009 Page 3ΣΔ ImplementationPractical Design Considerations• Internal node scaling & clipping• Effect of finite opamp gain & linearity• KT/C noise• Opamp noise• Finite opamp bandwidth• Opamp slew limited settling• Effect of comparator nonidealities• Power dissipation considerationsEECS 247- Lecture 24 Oversampled ADCs © 2009 Page 4Switched-Capacitor Implementation 2ndOrder ΣΔNodes Scaled for Maximum Dynamic Range• Modification (gain of ½ in front of integrators) reduce & optimize required signal range at the integrator outputs ~ 1.7x input full-scale (Δ)• Note: Non-idealities associated with 2ndintegrator and quantizer when referred to the ΣΔ input is attenuated by 1stintegrator high gainÆ The only building block requiring low-noise and high accuracy is the 1stintegratorRef: B.E. Boser and B.A. Wooley, “The Design of Sigma-Delta Modulation A/D Converters,”IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1298-1308, Dec. 1988.EECS 247- Lecture 24 Oversampled ADCs © 2009 Page 52ndOrder ΣΔ ModulatorExample: Switched-Capacitor ImplementationVINDout• Fully differential front-end• Two bottom-plate integrators• 1-bit DAC is made of switches and VrefsEECS 247- Lecture 24 Oversampled ADCs © 2009 Page 62ndOrder ΣΔ ModulatorSwitched-Capacitor ImplementationC2=2C1• The ½ loss in front of each integrator implemented by choice of:Æf0intg=fs /(4π)EECS 247- Lecture 24 Oversampled ADCs © 2009 Page 7Design Phase Simulations• Design of oversampled ADCs requires simulation of extremely long data traces due to the oversampled nature of the system• SPICE type simulators:– Normally used to test for gross circuit errors only – Too slow for detailed performance verification• Typically, behavioral modeling is used in MATLAB-like environments• Circuit non-idealities either computed or found by using SPICE at subcircuit level • Non-idealities introduced in the behavioral model one-by-one first to fully understand the effect of each individually• Next step is to add as many of the non-idealities simultaneously as possible to verify whether there are interaction among non-idealitiesEECS 247- Lecture 24 Oversampled ADCs © 2009 Page 8Testing of AFEAFEData Acq.PC MatlabfsFilteredSinwave• Typically in the design phase, provisions are made to test the AFE separate from Decimator• Output of the AFE (0,1) is acquired by a data acquisition board or logic analyzer • Matlab-like program is used to analyze data e.g. perform filtering & measure SNR, SNDR…..• During pre-silicon design phase, output of AFE is filtered in software & Matlab used to measure SNR, SNDREECS 247- Lecture 24 Oversampled ADCs © 2009 Page 9Example: Testing ΣΔ ADC2ndorder ΣΔM=256Analytical ExpressionMeasuredNote: The Nyquist ADC tests such as INL and DNL test do not apply to ΣΔmodulator type ADCSΣΔ testing is performed via SNDR as a function of input signal levelOverloadPointEECS 247- Lecture 24 Oversampled ADCs © 2009 Page 102ndOrder ΣΔEffect of 1stIntegrator Maximum Signal Handling Capability on SNR1stintegrator maximum signal handling:1.4, 1.5,1.6, and 1.7X Δ• Effect of 1stIntegrator maximum signal handling capability on converter SNRÆ No SNR loss for max. sig. handling >1.7ΔRef: B.E. Boser et. al, “The Design of Sigma-Delta Modulation A/D Converters,” JSSC, Dec. 1988.M=256– Behavioral model – Non-idealities tested one by oneEECS 247- Lecture 24 Oversampled ADCs © 2009 Page 112ndOrder ΣΔEffect of 2ndIntegrator Maximum Signal Handling Capability on SNR• Effect of 2nd Integrator maximum signal handling capability on SNRÆ Νο SNR loss for max. sig. handling >1.7ΔRef: B.E. Boser et. al, “The Design of Sigma-Delta Modulation A/D Converters,” JSSC, Dec. 1988.2nd integrator maximum signal handling:0.75,1,1.25, 1.5, and 1.7XΔEECS 247- Lecture 24 Oversampled ADCs © 2009 Page 122ndOrder ΣΔEffect of Integrator Finite DC GainVi-+φ1φ2aVoCsCI()()()111111111idealFinit DC GainCs zHzCIzazCsaCsCIHzCIazCsaCIHDC a−−−−=×−⎛⎞⎜⎟⎜⎟⎜⎟++⎝⎠=×⎛⎞⎜⎟+−⎜⎟⎜⎟++⎝⎠→=aÆ opamp gain at DCIntegratorEECS 247- Lecture 24 Oversampled ADCs © 2009 Page 131ndOrder ΣΔEffect of Integrator Finite DC Gain Analysis0P1aω=()Hω• Note: Quantization transfer function wrt output has integrator in the feedback path:0ωa()logHsIdeal Integ. (a=infinite)Integrator magnitude response+_eQDOUT∫()QQQDout 1e1HDout@ DC for ideal integ: 0eDout 1@ DC for real integ: eaω=+→=→≈EECS 247- Lecture 24 Oversampled ADCs © 2009 Page 141st& 2ndOrder ΣΔ Effect of Integrator Finite DC Gain• Low integrator DC gain Æ Increase in total in-band quantization noise • Can be shown: If a > M (oversampling ratio) Æ Insignificant degradation in SNR• Normally DC gain designed to be >> M in order to suppress nonlinearitiesf0 /aaMax signal levelEECS 247-
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