EE247 Lecture 7 Automatic on chip filter tuning continued from last lecture Continuous tuning continued Reference integrator locked to reference frequency DC tuning of resistive timing element Periodic digitally assisted filter tuning Systems where filter is followed by ADC DSP existing hardware can be used to periodically update filter freq response Continuous time filters Highpass filters Bandpass filters Lowpass to bandpass transformation Example 6th order bandpass filter Gm C BP filter using simple diff pair EECS 247 Lecture 7 Filters 2008 H K Page 1 Summary last lecture Continuous time filters Opamp MOSFET RC filters Gm C filters Frequency tuning for continuous time filters Trimming via fuses or laser Automatic on chip filter tuning Continuous tuning Utilizing VCF built with replica integrators Use of VCO built with replica integrators To be continued EECS 247 Lecture 7 Filters 2008 H K Page 2 Master Slave Frequency Tuning 3 Reference Integrator Locked to Reference Frequency Replica of main filter integrator Vin Gm I Gm Vref C Vref Vout Vtune Replica of main filter building block e g Gm C integrator used Utilizes the fact that a DC voltage source connected to the input of the Gm cell generates a constant current at the output proportional to the transconductance and the voltage reference I Gm Vref EECS 247 Lecture 7 Filters 2008 H K Page 3 Reference Integrator Locked to Reference Frequency Consider the following sequence Integrating capacitor is fully discharged t 0 Vin At t 0 the capacitor is connected to the output of the Gm cell for T amount of time then VC1 0 EECS 247 T t 0 VC1 Gm Vr ef T I Gm Vref Gm VC1 Vref C1 Vtune C1 QC1 VC1 C1 Gm Vref T VC1 Gm Vref T C1 time Lecture 7 Filters 2008 H K Page 4 Reference Integrator Locked to Reference Frequency Since at the end of the period T VC1 Gm Vref T I Gm Vref Gm C1 VC1 Vref CI If VC1 is forced to be equal to Vref then Vtune VC1 C T N Gm fclk VC1 Gm Vref T T time t 0 How do we manage to force VC1 Vref C1 Use feedback EECS 247 Lecture 7 Filters 2008 H K Page 5 Reference Integrator Locked to Reference Frequency Replica of main filter Gm S2 Vref S3 A Gm C1 S1 C2 Three clock phase operation To analyze study one phase at a time Ref A Durham J Hughes and W Redman White Circuit Architectures for High Linearity Monolithic Continuous Time Filtering IEEE Transactions on Circuits and Systems pp 651 657 Sept 1992 EECS 247 Lecture 7 Filters 2008 H K Page 6 Reference Integrator Locked to Reference Frequency P1 high S1 closed S2 S3 A Gm Vref S1 C1 C2 C1 discharged VC1 0 C2 retains its previous charge EECS 247 Lecture 7 Filters 2008 H K Page 7 Reference Integrator Locked to Reference Frequency P2 high S2 closed S2 Vref S3 A Gm I Gm Vref C1 C2 C1 charged with constant current I Gm Vref C2 retains its previous charge P2 VC1 Gm Vref T 2 C1 VC1 T1 EECS 247 T2 Lecture 7 Filters 2008 H K Page 8 Reference Integrator Locked to Reference Frequency P3 high S3 closed S3 V S2 Vref Gm C1 T1 C2 C1 charge shares with C2 Few cycles following startup Assuming A is large feedback forces V 0 VC2 Vref T2 EECS 247 A Lecture 7 Filters 2008 H K Page 9 Reference Integrator Locked to Reference Frequency P3 high S3 closed S2 Vref S3 A Gm C1 C2 VC1 VC2 V r ef T1 since VC1 Gm Vref T 2 T2 C1 t hen Vr ef Gm Vref T 2 or EECS 247 Lecture 7 Filters C1 Gm C1 T 2 N f cl k 2008 H K Page 10 Summary Replica Integrator Locked to Reference Frequency S2 Vref S3 A Gm C1 C2 Tuning Signal To Main Filter Feedback forces Gm to assume a value so that Integrator time constant locked to an accurate frequency Tuning signal used to adjust the time constant of the main filter integrators EECS 247 i nt g C1 Gm N f cl k or 0int g Gm C1 f cl k N Lecture 7 Filters 2008 H K Page 11 Issues 1 Loop Stability S2 Vref S3 A Gm C1 C2 Tuning Signal To Main Filter Note Need to pay attention to loop stability 9 C1 chosen to be smaller than C2 tradeoff between stability and speed of lock acquisition 9 Lowpass filter at the output of amplifier A helps stabilize the loop EECS 247 Lecture 7 Filters 2008 H K Page 12 Issues 2 GM Cell DC Offset Induced Error Problems to be aware of S2 Vref S3 A Gm C1 C2 To Main Filter 0int g Gm C1 fc l k N Tuning error due to master integrator DC offset EECS 247 Lecture 7 Filters 2008 H K Page 13 Issues Gm Cell DC Offset What is DC offset Simple example For the differential pair shown here mismatch in input device or load characteristics would cause DC offset Vo 0 requires a non zero input voltage Offset could be modeled as a small DC voltage source at the input for which with shorted inputs Vo 0 Vo Vos Vin M1 M2 Vtune Example Differential Pair EECS 247 Lecture 7 Filters 2008 H K Page 14 Simple Gm Cell DC Offset Mismatch associated with M1 M2 DC offset W L M 1 2 1 Vos Vth1 Vth2 Vov1 2 W 2 L M 1 2 Vo Vos M1 Vin M2 Vtune Assuming offset due to load device mismatch is negligible Ref Gray Hurst Lewis Meyer Analysis Design of Analog Integrated Circuits Wiley 2001 page 335 EECS 247 Lecture 7 Filters 2008 H K Page 15 Gm Cell Offset Induced Error Voltage source representing DC offset Vos Vref S2 S3 A Gm I Gm Vref Vos C1 C2 Effect of Gm cell DC offset VC1 VC2 V re f I de al VC1 G m Vre f T 2 C1 with o ffse t VC1 G m Vre f Vos T 2 C1 V C1 T 2 1 os or Gm Vre f EECS 247 Lecture 7 Filters 2008 H K Page 16 Gm Cell Offset Induced Error Vos S2 S3 A Gm Vref I Gm Vref Vos C1 C2 Example V T 2 1 os fcrit ical Gm Gm C1 V ref V C1 f or o s 1 1 0 0 9T 2 0 9 N Gm f cl k Vr ef C1 1 0 er r o r i n t u n i n g EECS 247 Lecture 7 Filters 2008 H K Page 17 Gm Cell Tuning Offset Induced Error Solution Assuming differential integrator Add a pair of auxiliary inputs to the input stage for offset cancellation purposes Cint g Vo Vinaux Aux Main Input Input EECS 247 Vinmain Lecture 7 Filters M3 M1 M4 M2 2008 H K Page 18 Simple Gm Cell AC Small Signal Model Vo M1 M3 gM1Vin1gm Vin1 gmVo Vin2 Vin1 M1 2Cintg Vin1 M1 M3 g m Vin1 g m …
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